Modularized project; mux, clock, and reg done; Progress on RegFile

lab2CA.srcs/sources_1/new/RegFile.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 02/15/2019 12:21:16 PM
+// Design Name: 
+// Module Name: RegFile
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module RegFile(input wire clk, reset,
+                input wire [1:0] write_index, op0_idx, op1_idx,
+                input wire [8:0] write_data,
+                output wire [8:0] op0, op1);
+    
+    wire [8:0] r0_out, r1_out, r2_out, r3_out;
+    
+    // To select a register En input must be 2'b00
+    
+    register r0(
+        .clk(clk),
+        .reset(reset),
+        .En({write_index[0], write_index[1]}),
+        .Din(write_data),
+        .Dout(r0_out));
+        
+    register r1(
+        .clk(clk),
+        .reset(reset),
+        .En({write_index[0], ~write_index[1]}),
+        .Din(write_data),
+        .Dout(r1_out));
+        
+    register r2(
+        .clk(clk),
+        .reset(reset),
+        .En({~write_index[0], write_index[1]}),
+        .Din(write_data),
+        .Dout(r2_out));
+        
+    register r3(
+        .clk(clk),
+        .reset(reset),
+        .En({~write_index[0], ~write_index[1]}),
+        .Din(write_data),
+        .Dout(r3_out));    
+        
+    mux m0(
+        .A(r0_out),
+        .B(r1_out),
+        .C(r2_out),
+        .D(r3_out),
+        .switch(op0_idx));
+        
+    mux m1(
+        .A(r0_out),
+        .B(r1_out),
+        .C(r2_out),
+        .D(r3_out),
+        .switch(op1_idx));
+    
+endmodule