Modularized project; mux, clock, and reg done; Progress on RegFile

lab2CA.srcs/sources_1/new/lab2testing.v

@@ -3,7 +3,6 @@
 
 
 module lab2testing();
-
 endmodule
 
 module regFile(input wire clk, reset,
@@ -13,6 +12,8 @@ module regFile(input wire clk, reset,
     
     wire [8:0] r0_out, r1_out, r2_out, r3_out;
     
+    // To select a register En input must be 2'b00
+    
     register r0(
         .clk(clk),
         .reset(reset),
@@ -55,21 +56,4 @@ module regFile(input wire clk, reset,
         .D(r3_out),
         .switch(op1_idx));
     
-endmodule
-
-module register(input wire clk, reset,
-                input wire [1:0] En,
-                input wire [8:0] Din,
-                output reg [8:0] Dout);
-
-endmodule
-
-module MUX();
-
-endmodule
-
-module fetchUnit(input wire clk,
-                 input wire [8:0] AddrIn,
-                 output wire [8:0] AddrOut);
-
-endmodule
+endmodule