new thing

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -164,9 +164,6 @@ module gen_clock();
     end
 endmodule
 
-
-//To enable register, input 00 to En, register is always outputting contents
-
 module mux_2_1(input wire switch,
            input wire [8:0] A,B,
            output reg [8:0] out);
@@ -426,13 +423,13 @@ module register(input wire clk, reset,
                 
     always @(posedge clk) begin
         if (reset == 1'b1) begin
-            Dout <= 9'b000000000;
+            Dout = 9'b000000000;
         end
         else if (En == 2'b00) begin
-            Dout <= Din;
+            Dout = Din;
         end
         else begin
-            Dout <= "ZZZZZZZZZ";
+            Dout = "ZZZZZZZZZ";
         end
     end
 
@@ -489,7 +486,7 @@ module sub_9bit(
     
     twos_compliment_9bit two_comp0(
         .A(B),
-        .C(D));
+        .B(D));
     
     add_9bit add0(
         .A(A),