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jose.rodriguezlabra
2019-02-16 13:04:06 -05:00
parent 0d9cc2b890
commit 84e3725fdb
13 changed files with 126 additions and 44 deletions
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25
lab2CA.cache/wt/webtalk_pa.xml
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@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Sat Feb 16 12:49:45 2019"> <application name="pa" timeStamp="Sat Feb 16 13:03:32 2019">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="88e779ed22f94d2db93b335d17c75f15" type="ProjectID"/> <property name="ProjectID" value="88e779ed22f94d2db93b335d17c75f15" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/> <property name="ProjectIteration" value="1" type="ProjectIteration"/>
@@ -17,25 +17,26 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/> <property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item> </item>
<item name="Java Command Handlers"> <item name="Java Command Handlers">
<property name="RunSynthesis" value="7" type="JavaHandler"/> <property name="RunSynthesis" value="12" type="JavaHandler"/>
<property name="ShowView" value="3" type="JavaHandler"/> <property name="ShowView" value="6" type="JavaHandler"/>
</item> </item>
<item name="Gui Handlers"> <item name="Gui Handlers">
<property name="BaseDialog_CANCEL" value="3" type="GuiHandlerData"/> <property name="BaseDialog_CANCEL" value="4" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="9" type="GuiHandlerData"/> <property name="BaseDialog_OK" value="17" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="6" type="GuiHandlerData"/> <property name="FileSetPanel_FILE_SET_PANEL_TREE" value="12" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="8" type="GuiHandlerData"/> <property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="13" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="1" type="GuiHandlerData"/> <property name="HCodeEditor_CLOSE" value="2" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="4" type="GuiHandlerData"/>
<property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="2" type="GuiHandlerData"/> <property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="2" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="3" type="GuiHandlerData"/> <property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="10" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="1" type="GuiHandlerData"/> <property name="PAViews_CODE" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/> <property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_SAVE" value="1" type="GuiHandlerData"/> <property name="SaveProjectUtils_SAVE" value="2" type="GuiHandlerData"/>
</item> </item>
<item name="Other"> <item name="Other">
<property name="GuiMode" value="33" type="GuiMode"/> <property name="GuiMode" value="34" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/> <property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="28" type="TclMode"/> <property name="TclMode" value="29" type="TclMode"/>
</item> </item>
</section> </section>
</application> </application>

8
lab2CA.runs/.jobs/vrs_config_10.xml Normal file
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

8
lab2CA.runs/.jobs/vrs_config_11.xml Normal file
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

8
lab2CA.runs/.jobs/vrs_config_12.xml Normal file
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

8
lab2CA.runs/.jobs/vrs_config_13.xml Normal file
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

8
lab2CA.runs/.jobs/vrs_config_9.xml Normal file
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

53
lab2CA.runs/synth_1/ALU.vds
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@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit) # Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Feb 16 12:49:31 2019 # Start of session at: Sat Feb 16 13:03:34 2019
# Process ID: 18228 # Process ID: 11092
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1 # Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log ALU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl # Command line: vivado.exe -log ALU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/ALU.vds # Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/ALU.vds
@@ -15,9 +15,9 @@ Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti' Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: Launching helper process for spawning children vivado processes INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 8848 INFO: Helper process launched with PID 18316
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 363.309 ; gain = 101.105 Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 363.020 ; gain = 100.695
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3] INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:15] INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:15]
@@ -25,25 +25,40 @@ INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/JoseIgnacio/CA Lab
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (1#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (1#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (2#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:15] INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (2#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:15]
WARNING: [Synth 8-350] instance 'add0' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:14] WARNING: [Synth 8-350] instance 'add0' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:14]
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:483] INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:480]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:490] INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:499]
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:502] INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316]
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:319] INFO: [Synth 8-6157] synthesizing module 'not_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:308]
INFO: [Synth 8-6157] synthesizing module 'not_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:311] INFO: [Synth 8-6155] done synthesizing module 'not_1bit' (3#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:308]
INFO: [Synth 8-6155] done synthesizing module 'not_1bit' (3#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:311] INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (4#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316]
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (4#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:319] WARNING: [Synth 8-350] instance 'add0' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:509]
WARNING: [Synth 8-350] instance 'add0' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:512] INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (5#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:499]
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (5#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:502] WARNING: [Synth 8-350] instance 'add0' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:491]
ERROR: [Synth 8-448] named port connection 'C' does not exist for instance 'two_comp0' of module 'twos_compliment_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:492] INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (6#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:480]
WARNING: [Synth 8-350] instance 'add0' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:494] INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:367]
ERROR: [Synth 8-6156] failed synthesizing module 'sub_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:483] INFO: [Synth 8-6157] synthesizing module 'or_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:358]
INFO: [Synth 8-6155] done synthesizing module 'or_1bit' (7#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:358]
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (8#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:367]
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:256]
INFO: [Synth 8-6157] synthesizing module 'nor_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:247]
INFO: [Synth 8-6155] done synthesizing module 'nor_1bit' (9#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:247]
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (10#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:256]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:35]
INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:105]
INFO: [Synth 8-6157] synthesizing module 'and_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:96]
INFO: [Synth 8-6155] done synthesizing module 'and_1bit' (11#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:96]
INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (12#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:105]
ERROR: [Synth 8-448] named port connection 'Cin' does not exist for instance 'and0' of module 'and_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:38]
ERROR: [Synth 8-448] named port connection 'Sum' does not exist for instance 'and0' of module 'and_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:39]
INFO: [Synth 8-6157] synthesizing module 'shift_logical_left' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:462]
ERROR: [Synth 8-6156] failed synthesizing module 'shift_logical_left' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:462]
ERROR: [Synth 8-6156] failed synthesizing module 'ALU' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3] ERROR: [Synth 8-6156] failed synthesizing module 'ALU' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 419.434 ; gain = 157.230 Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 419.512 ; gain = 157.188
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
synthesize failed synthesize failed
INFO: [Common 17-83] Releasing license: Synthesis INFO: [Common 17-83] Releasing license: Synthesis
14 Infos, 4 Warnings, 0 Critical Warnings and 4 Errors encountered. 28 Infos, 4 Warnings, 0 Critical Warnings and 5 Errors encountered.
synth_design failed synth_design failed
ERROR: [Common 17-69] Command failed: Vivado Synthesis failed ERROR: [Common 17-69] Command failed: Vivado Synthesis failed
INFO: [Common 17-206] Exiting Vivado at Sat Feb 16 12:49:41 2019... INFO: [Common 17-206] Exiting Vivado at Sat Feb 16 13:03:44 2019...

2
lab2CA.runs/synth_1/gen_run.xml
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550339368"> <GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550340212">
<File Type="PA-TCL" Name="ALU.tcl"/> <File Type="PA-TCL" Name="ALU.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="ALU_drc_synth.rpt"/> <File Type="RDS-PROPCONSTRS" Name="ALU_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="ALU_reports.tcl"/> <File Type="REPORTS-TCL" Name="ALU_reports.tcl"/>

4
lab2CA.runs/synth_1/vivado.jou
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@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit) # Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Feb 16 12:49:31 2019 # Start of session at: Sat Feb 16 13:03:34 2019
# Process ID: 18228 # Process ID: 11092
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1 # Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log ALU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl # Command line: vivado.exe -log ALU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/ALU.vds # Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/ALU.vds

BIN
lab2CA.runs/synth_1/vivado.pb
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Binary file not shown.

11
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -164,9 +164,6 @@ module gen_clock();
end end
endmodule endmodule
//To enable register, input 00 to En, register is always outputting contents
module mux_2_1(input wire switch, module mux_2_1(input wire switch,
input wire [8:0] A,B, input wire [8:0] A,B,
output reg [8:0] out); output reg [8:0] out);
@@ -426,13 +423,13 @@ module register(input wire clk, reset,
always @(posedge clk) begin always @(posedge clk) begin
if (reset == 1'b1) begin if (reset == 1'b1) begin
Dout <= 9'b000000000; Dout = 9'b000000000;
end end
else if (En == 2'b00) begin else if (En == 2'b00) begin
Dout <= Din; Dout = Din;
end end
else begin else begin
Dout <= "ZZZZZZZZZ"; Dout = "ZZZZZZZZZ";
end end
end end
@@ -489,7 +486,7 @@ module sub_9bit(
twos_compliment_9bit two_comp0( twos_compliment_9bit two_comp0(
.A(B), .A(B),
.C(D)); .B(D));
add_9bit add0( add_9bit add0(
.A(A), .A(A),

6
vivado.jou
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@@ -2,10 +2,10 @@
# Vivado v2018.3 (64-bit) # Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Feb 16 12:39:38 2019 # Start of session at: Sat Feb 16 12:51:25 2019
# Process ID: 15076 # Process ID: 14124
# Current directory: C:/Users/JoseIgnacio/CA Lab # Current directory: C:/Users/JoseIgnacio/CA Lab
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent16632 C:\Users\JoseIgnacio\CA Lab\lab2CA.xpr # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent19396 C:\Users\JoseIgnacio\CA Lab\lab2CA.xpr
# Log file: C:/Users/JoseIgnacio/CA Lab/vivado.log # Log file: C:/Users/JoseIgnacio/CA Lab/vivado.log
# Journal file: C:/Users/JoseIgnacio/CA Lab\vivado.jou # Journal file: C:/Users/JoseIgnacio/CA Lab\vivado.jou
#----------------------------------------------------------- #-----------------------------------------------------------

29
vivado_15076.backup.jou Normal file
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@@ -0,0 +1,29 @@
#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Feb 16 12:39:38 2019
# Process ID: 15076
# Current directory: C:/Users/JoseIgnacio/CA Lab
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent16632 C:\Users\JoseIgnacio\CA Lab\lab2CA.xpr
# Log file: C:/Users/JoseIgnacio/CA Lab/vivado.log
# Journal file: C:/Users/JoseIgnacio/CA Lab\vivado.jou
#-----------------------------------------------------------
start_gui
open_project {C:/Users/JoseIgnacio/CA Lab/lab2CA.xpr}
update_compile_order -fileset sources_1
reset_run synth_1
launch_runs synth_1 -jobs 4
wait_on_run synth_1
reset_run synth_1
launch_runs synth_1 -jobs 4
wait_on_run synth_1
reset_run synth_1
launch_runs synth_1 -jobs 4
wait_on_run synth_1
reset_run synth_1
launch_runs synth_1 -jobs 4
wait_on_run synth_1
reset_run synth_1
launch_runs synth_1 -jobs 4
wait_on_run synth_1