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Added 9-bit AND module

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WilliamMiceli
2019-02-15 15:13:40 -05:00
parent 2a84458894
commit 8b37bee087
1 changed files with 53 additions and 1 deletions
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54
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -93,7 +93,7 @@ module adder_9bit(
endmodule endmodule
module and_gate( module and_1bit(
input wire A, input wire A,
input wire B, input wire B,
output wire C); output wire C);
@@ -102,6 +102,58 @@ module and_gate(
endmodule endmodule
module and_9bit(
input wire [8:0] A,
input wire [8:0] B,
output wire [8:0] C);
and_1bit and0(
.A(A[0])
.B(B[0])
.C(C[0]));
and_1bit and1(
.A(A[1])
.B(B[1])
.C(C[1]));
and_1bit and2(
.A(A[2])
.B(B[2])
.C(C[2]));
and_1bit and3(
.A(A[3])
.B(B[3])
.C(C[3]));
and_1bit and4(
.A(A[4])
.B(B[4])
.C(C[4]));
and_1bit and5(
.A(A[5])
.B(B[5])
.C(C[5]));
and_1bit and6(
.A(A[6])
.B(B[6])
.C(C[6]));
and_1bit and7(
.A(A[7])
.B(B[7])
.C(C[7]));
and_1bit and8(
.A(A[8])
.B(B[8])
.C(C[8]));
endmodule
module gen_clock(); module gen_clock();
reg clk; reg clk;