Added inverter

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -14,6 +14,13 @@ module gen_clock();
 
 endmodule
 
+module inverter(
+    input wire A,
+    output wire B);
+    
+    assign B = ~A;
+endmodule
+
 module mux(input wire [1:0] switch,
            input wire [8:0] A,B,C,D,
            output reg [8:0] out);