Small formatting change

lab2CA.srcs/sources_1/new/CPU9bits.v

@@ -1,8 +1,9 @@
 `timescale 1ns / 1ps
 
-module CPU9bits(input wire [8:0] instr,
-        input wire reset, clk,
-        output wire done
+module CPU9bits(
+    input wire [8:0] instr,
+    input wire reset, clk,
+    output wire done
     );
     
     wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut;