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Small formatting change

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WilliamMiceli
2019-03-16 13:44:44 -04:00
parent b621f5a46b
commit 934c73e899
1 changed files with 4 additions and 3 deletions
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7
lab2CA.srcs/sources_1/new/CPU9bits.v
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@@ -1,8 +1,9 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
module CPU9bits(input wire [8:0] instr, module CPU9bits(
input wire reset, clk, input wire [8:0] instr,
output wire done input wire reset, clk,
output wire done
); );
wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut; wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut;