Small formatting change

lab2CA.srcs/sources_1/new/CPU9bits.v

@@ -1,6 +1,7 @@
 `timescale 1ns / 1ps
 
-module CPU9bits(input wire [8:0] instr,
+module CPU9bits(
+    input wire [8:0] instr,
     input wire reset, clk,
     output wire done
     );