Stopped Vivado from whinning

lab2CA.srcs/sources_1/new/CPU9bits.v

@@ -203,7 +203,6 @@ endmodule
 
 module CPU9bits_tb();
     reg clk, reset;
-    reg [8:0] result;
     wire done;
 
     always
@@ -212,7 +211,8 @@ module CPU9bits_tb();
     CPU9bits CPU9bits0(
         .reset(reset),
         .clk(clk),
-        .done(done)
+        .done(done),
+        .result()
         );
         
     initial begin
@@ -220,6 +220,8 @@ module CPU9bits_tb();
         reset = 1'b1;
         #5
         reset = 1'b0;
+        #5
+        reset = 1'b1;
     
 //        instruction = 9'b000100000;
 //        reset = 1'b1;