Renamed mux in case we need different kinds later on

2019-02-15 14:56:34 -05:00
parent 3d8ae740f0
commit 9eec4cdc76
1 changed files with 1 additions and 1 deletions
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -34,7 +34,7 @@ module inverter(

 endmodule

-module mux(input wire [1:0] switch,
+module mux_4_1(input wire [1:0] switch,
           input wire [8:0] A,B,C,D,
           output reg [8:0] out);