Nonsense

lab2CA.srcs/sources_1/new/ControlUnit.v

@@ -6,24 +6,15 @@ module ControlUnit(
     output reg [3:0] aluOut,
     output reg [2:0] FU,
     output reg [1:0] bank,
-<<<<<<< Updated upstream
-    output reg addi, mem, dataMemEn, RegEn, halt, link, js
-    );
-=======
     output reg addi, mem, dataMemEn, RegEn, halt, link, js, compare0, compare1
-        );
->>>>>>> Stashed changes
+    );
     
     always @(instIn, functBit)
     begin
         case(instIn)
         4'b0000: // Halt/NOP
             begin 
-<<<<<<< Updated upstream
             halt <= functBit;
-=======
-            halt <= ~functBit;
->>>>>>> Stashed changes
             RegEn <= 1'b1; 
             FU <= 3'b001; // Disable Branching
             addi <= 1'b0;