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Removed my behavioral slt

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This commit is contained in:
Johannes
2019-03-12 21:33:24 -04:00
parent 735970454a
commit a9a4e81c6c
3 changed files with 24 additions and 64 deletions
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40
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -943,46 +943,6 @@ module shift_right_arithmetic_tb();
end
endmodule
module slt (
input wire en,
input wire [8:0] inA, inB,
output reg [8:0] outA);
always @(inA, inB)begin
if (inA < inB) begin
outA = 9'b000000001;
end
else begin
outA = 9'b000000000;
end
end
endmodule
//testbench
module slt_tb();
reg [8:0] indexA;
reg [8:0] indexB;
wire outputA;
slt slt0(
.inA(indexA),
.inB(indexB),
.outA(outputA));
initial begin
indexA = 9'b000000000;
indexB = 9'b000000000;
#10
indexA = 9'b000000000;
indexB = 9'b111100000;
#10
indexA = 9'b000001111;
indexB = 9'b000000000;
#10
$finish;
end
endmodule
module sub_9bit(
input wire [8:0] A,
input wire [8:0] B,

2
lab2CA.srcs/sources_1/new/ControlUnit.v
View File

@@ -44,7 +44,7 @@ module ControlUnit(
RegEn <= 1'b0;
end
4'b0111: begin
aluOut <= 4'b1001; //slt
aluOut <= 4'b1001; //Less than
RegEn <= 1'b0;
end
4'b0110: begin