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Registers and Banks don't need an enable, should be ignored using MUXes

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This commit is contained in:
WilliamMiceli
2019-03-29 18:10:13 -04:00
parent 78f481f724
commit acf7f9e92b
3 changed files with 67 additions and 57 deletions
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31
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -259,43 +259,32 @@ module comparator_tb();
endmodule
module decoder (
input wire en,
input wire [1:0] index,
output reg [3:0] regOut);
always @(en, index)begin
if(en == 0)begin
case(index)
2'b00: regOut <= 4'b1110;
2'b01: regOut <= 4'b1101;
2'b10: regOut <= 4'b1011;
2'b11: regOut <= 4'b0111;
default: regOut <= 4'b1111;
endcase
end
else begin
regOut <= 4'b1111;
end
end
always @ (index)
case(index)
2'b00: regOut <= 4'b1110;
2'b01: regOut <= 4'b1101;
2'b10: regOut <= 4'b1011;
2'b11: regOut <= 4'b0111;
default: regOut <= 4'b1111;
endcase
endmodule
//testbench
module decoder_tb();
reg enable;
reg [1:0] indexIn;
wire [3:0] regOut;
decoder dec0(
.en(enable),
.index(indexIn),
.regOut(regOut));
.regOut(regOut)
);
initial begin
enable = 0;
indexIn = 2'b00;
#5
enable = 1;
#5
indexIn = 2'b01;
#5
indexIn = 2'b10;

86
lab2CA.srcs/sources_1/new/CPU9bits.v
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@@ -2,20 +2,21 @@
module CPU9bits(
input wire reset, clk,
output reg [8:0] result,
output wire done
);
wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N, bankData, bankOP,jumpNeg;
wire [2:0] FU;
wire [3:0] aluOp;
wire [2:0] FU;
wire [1:0] bankS;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link, js, dataMemEn;
instructionMemory iM(
.address(PCout),
.readData(instr)
);
dataMemory dM(
.clk(clk),
.writeEnable(dataMemEn),
@@ -23,11 +24,10 @@ module CPU9bits(
.address(op1),
.readData(dataMemOut)
);
RegFile RF(
.clk(clk),
.reset(reset),
.enable(RegEn),
.write_index(instr[4:3]),
.op0_idx(instr[4:3]),
.op1_idx(instr[2:1]),
@@ -35,11 +35,10 @@ module CPU9bits(
.op0(op0),
.op1(op1)
);
RegFile Bank(
.clk(clk),
.reset(reset),
.enable(bankS[1]),
.write_index(instr[2:1]),
.op0_idx(instr[2:1]),
.op1_idx(2'b00),//Doesn't matter
@@ -47,7 +46,7 @@ module CPU9bits(
.op0(bankOP),
.op1()
);
FetchUnit FetchU(
.clk(clk),
.reset(reset),
@@ -55,14 +54,14 @@ module CPU9bits(
.AddrIn(FUAddr),
.AddrOut(PCout)
);
ALU alu(
.opcode(aluOp),
.operand0(op0),
.operand1(op1),
.result(AluOut)
);
ControlUnit CU(
.instIn(instr[8:5]),
.functBit(instr[0]),
@@ -77,10 +76,10 @@ module CPU9bits(
.bank(bankS),
.js(js)
);
//-----------------------Fetch Unit Stuff
add_9bit JBAdder(
.A(PCout),
.B(JBRes),
@@ -88,47 +87,47 @@ module CPU9bits(
.Sum(FUJB),
.Cout(cout0)
);
mux_2_1 mux0(
.A(op0),
.B(FUJB),
.out(FUAddr),
.switch(FU[1])
);
twos_compliment_9bit two_comp0(
.A({4'b0000,instr[4:0]}),
.B(jumpNeg)
);
mux_2_1 mux1(
.A({4'b0000,instr[4:0]}),
.B(jumpNeg),
.out(SE2N),
.switch(js)
);
mux_2_1 mux2(
.A(SE2N), //Jump -- Change with signer module!
.B(SE1N),//Branch -- Change with signer module!
.out(JBRes),
.switch(FU[2])
);
sign_extend_3bit SE1(
.A(instr[2:0]),
.B(SE1N)
);
bit1_mux_2_1 BranMux( // BEQ MUX
.A(FU[0]),
.B(AluOut[0]),
.out(fetchBranch),
.switch(FU[2]) // FU[2] only goes high when BEQ
);
///--------------------------Addi Stuff
add_9bit Addier(
.A(SE3N), // Change with signer module!
.B(op0),
@@ -136,19 +135,19 @@ module CPU9bits(
.Sum(AddiOut),
.Cout(cout1)
);
sign_extend_3bit SE3(
.A(instr[2:0]),
.B(SE3N)
);
mux_2_1 mux3(
.A(AluOut),
.B(AddiOut),
.out(loadMux),
.switch(addiS)
);
///--------------------------Mem stuff
mux_2_1 mux4(
@@ -157,26 +156,51 @@ module CPU9bits(
.out(bankData),
.switch(loadS)
);
///--------------------------Bank stuff
mux_2_1 mux5(
.A(bankData),
.B(bankOP),
.out(RFIn),
.switch(bankS[0])
);
///--------------------------Link Stuff
mux_2_1 mux6(
.A(loadMux),
.B(PCout),
.out(linkData),
.switch(link)
);
always @ (instr, op0, op1)
begin
case(instr[8:5])
4'b0001: // Load Byte
result <= dataMemOut;
4'b0011: // Link
result <= linkData;
4'b0101: // Add/Subtract
result <= AluOut;
4'b0110: // Add Immediate
result <= AddiOut;
4'b0111: // Set if Less Than
result <= AluOut;
4'b1010: // Bank Load/Bank Store
result <= RFIn;
4'b1101: // NOR
result <= AluOut;
4'b1110: // OR/AND
result <= AluOut;
4'b1111: // Shift Right Logical/Shift Left Logical
result <= AluOut;
default:
result <= 9'bXXXXXXXXX;
endcase
end
endmodule
module CPU9bits_tb();

7
lab2CA.srcs/sources_1/new/RegFile.v
View File

@@ -1,6 +1,6 @@
`timescale 1ns / 1ps
module RegFile(input wire clk, reset, enable,
module RegFile(input wire clk, reset,
input wire [1:0] write_index, op0_idx, op1_idx,
input wire [8:0] write_data,
output wire [8:0] op0, op1);
@@ -11,7 +11,6 @@ module RegFile(input wire clk, reset, enable,
// To select a register En input must be 2'b00
decoder d0(
.en(enable),
.index(write_index),
.regOut(decOut)
);
@@ -67,7 +66,7 @@ endmodule
module regFile_tb();
reg [8:0] write_d;
reg [1:0] w_idx, op0_idx, op1_idx;
reg reset,clk, enable;
reg reset,clk;
wire [8:0] op0,op1;
initial begin
@@ -79,7 +78,6 @@ module regFile_tb();
RegFile regFile0(
.clk(clk),
.enable(enable),
.reset(reset),
.write_index(w_idx),
.op0_idx(op0_idx),
@@ -94,7 +92,6 @@ module regFile_tb();
reset = 1;
#5
reset = 0;
enable = 1;
w_idx = 2'b00;
op0_idx = 2'b00;
op1_idx = 2'b00;