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Registers and Banks don't need an enable, should be ignored using MUXes

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WilliamMiceli
2019-03-29 18:10:13 -04:00
parent 78f481f724
commit acf7f9e92b
3 changed files with 67 additions and 57 deletions
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31
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -259,43 +259,32 @@ module comparator_tb();
endmodule
module decoder (
input wire en,
input wire [1:0] index,
output reg [3:0] regOut);
always @(en, index)begin
if(en == 0)begin
case(index)
2'b00: regOut <= 4'b1110;
2'b01: regOut <= 4'b1101;
2'b10: regOut <= 4'b1011;
2'b11: regOut <= 4'b0111;
default: regOut <= 4'b1111;
endcase
end
else begin
regOut <= 4'b1111;
end
end
always @ (index)
case(index)
2'b00: regOut <= 4'b1110;
2'b01: regOut <= 4'b1101;
2'b10: regOut <= 4'b1011;
2'b11: regOut <= 4'b0111;
default: regOut <= 4'b1111;
endcase
endmodule
//testbench
module decoder_tb();
reg enable;
reg [1:0] indexIn;
wire [3:0] regOut;
decoder dec0(
.en(enable),
.index(indexIn),
.regOut(regOut));
.regOut(regOut)
);
initial begin
enable = 0;
indexIn = 2'b00;
#5
enable = 1;
#5
indexIn = 2'b01;
#5
indexIn = 2'b10;