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Registers and Banks don't need an enable, should be ignored using MUXes

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WilliamMiceli
2019-03-29 18:10:13 -04:00
parent 78f481f724
commit acf7f9e92b
3 changed files with 67 additions and 57 deletions
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31
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -259,43 +259,32 @@ module comparator_tb();
endmodule endmodule
module decoder ( module decoder (
input wire en,
input wire [1:0] index, input wire [1:0] index,
output reg [3:0] regOut); output reg [3:0] regOut);
always @(en, index)begin always @ (index)
if(en == 0)begin case(index)
case(index) 2'b00: regOut <= 4'b1110;
2'b00: regOut <= 4'b1110; 2'b01: regOut <= 4'b1101;
2'b01: regOut <= 4'b1101; 2'b10: regOut <= 4'b1011;
2'b10: regOut <= 4'b1011; 2'b11: regOut <= 4'b0111;
2'b11: regOut <= 4'b0111; default: regOut <= 4'b1111;
default: regOut <= 4'b1111; endcase
endcase
end
else begin
regOut <= 4'b1111;
end
end
endmodule endmodule
//testbench //testbench
module decoder_tb(); module decoder_tb();
reg enable;
reg [1:0] indexIn; reg [1:0] indexIn;
wire [3:0] regOut; wire [3:0] regOut;
decoder dec0( decoder dec0(
.en(enable),
.index(indexIn), .index(indexIn),
.regOut(regOut)); .regOut(regOut)
);
initial begin initial begin
enable = 0;
indexIn = 2'b00; indexIn = 2'b00;
#5 #5
enable = 1;
#5
indexIn = 2'b01; indexIn = 2'b01;
#5 #5
indexIn = 2'b10; indexIn = 2'b10;

30
lab2CA.srcs/sources_1/new/CPU9bits.v
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@@ -2,12 +2,13 @@
module CPU9bits( module CPU9bits(
input wire reset, clk, input wire reset, clk,
output reg [8:0] result,
output wire done output wire done
); );
wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N, bankData, bankOP,jumpNeg; wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N, bankData, bankOP,jumpNeg;
wire [2:0] FU;
wire [3:0] aluOp; wire [3:0] aluOp;
wire [2:0] FU;
wire [1:0] bankS; wire [1:0] bankS;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link, js, dataMemEn; wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link, js, dataMemEn;
@@ -27,7 +28,6 @@ module CPU9bits(
RegFile RF( RegFile RF(
.clk(clk), .clk(clk),
.reset(reset), .reset(reset),
.enable(RegEn),
.write_index(instr[4:3]), .write_index(instr[4:3]),
.op0_idx(instr[4:3]), .op0_idx(instr[4:3]),
.op1_idx(instr[2:1]), .op1_idx(instr[2:1]),
@@ -39,7 +39,6 @@ module CPU9bits(
RegFile Bank( RegFile Bank(
.clk(clk), .clk(clk),
.reset(reset), .reset(reset),
.enable(bankS[1]),
.write_index(instr[2:1]), .write_index(instr[2:1]),
.op0_idx(instr[2:1]), .op0_idx(instr[2:1]),
.op1_idx(2'b00),//Doesn't matter .op1_idx(2'b00),//Doesn't matter
@@ -176,6 +175,31 @@ module CPU9bits(
.switch(link) .switch(link)
); );
always @ (instr, op0, op1)
begin
case(instr[8:5])
4'b0001: // Load Byte
result <= dataMemOut;
4'b0011: // Link
result <= linkData;
4'b0101: // Add/Subtract
result <= AluOut;
4'b0110: // Add Immediate
result <= AddiOut;
4'b0111: // Set if Less Than
result <= AluOut;
4'b1010: // Bank Load/Bank Store
result <= RFIn;
4'b1101: // NOR
result <= AluOut;
4'b1110: // OR/AND
result <= AluOut;
4'b1111: // Shift Right Logical/Shift Left Logical
result <= AluOut;
default:
result <= 9'bXXXXXXXXX;
endcase
end
endmodule endmodule

7
lab2CA.srcs/sources_1/new/RegFile.v
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@@ -1,6 +1,6 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
module RegFile(input wire clk, reset, enable, module RegFile(input wire clk, reset,
input wire [1:0] write_index, op0_idx, op1_idx, input wire [1:0] write_index, op0_idx, op1_idx,
input wire [8:0] write_data, input wire [8:0] write_data,
output wire [8:0] op0, op1); output wire [8:0] op0, op1);
@@ -11,7 +11,6 @@ module RegFile(input wire clk, reset, enable,
// To select a register En input must be 2'b00 // To select a register En input must be 2'b00
decoder d0( decoder d0(
.en(enable),
.index(write_index), .index(write_index),
.regOut(decOut) .regOut(decOut)
); );
@@ -67,7 +66,7 @@ endmodule
module regFile_tb(); module regFile_tb();
reg [8:0] write_d; reg [8:0] write_d;
reg [1:0] w_idx, op0_idx, op1_idx; reg [1:0] w_idx, op0_idx, op1_idx;
reg reset,clk, enable; reg reset,clk;
wire [8:0] op0,op1; wire [8:0] op0,op1;
initial begin initial begin
@@ -79,7 +78,6 @@ module regFile_tb();
RegFile regFile0( RegFile regFile0(
.clk(clk), .clk(clk),
.enable(enable),
.reset(reset), .reset(reset),
.write_index(w_idx), .write_index(w_idx),
.op0_idx(op0_idx), .op0_idx(op0_idx),
@@ -94,7 +92,6 @@ module regFile_tb();
reset = 1; reset = 1;
#5 #5
reset = 0; reset = 0;
enable = 1;
w_idx = 2'b00; w_idx = 2'b00;
op0_idx = 2'b00; op0_idx = 2'b00;
op1_idx = 2'b00; op1_idx = 2'b00;