Registers and Banks don't need an enable, should be ignored using MUXes

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -259,12 +259,10 @@ module comparator_tb();
 endmodule
 
 module decoder (
-    input wire en,
     input wire [1:0] index,
     output reg [3:0] regOut);
     
-    always @(en, index)begin
-        if(en == 0)begin
+    always @ (index)
     case(index) 
         2'b00: regOut <= 4'b1110; 
         2'b01: regOut <= 4'b1101;
@@ -272,30 +270,21 @@ module decoder (
         2'b11: regOut <= 4'b0111;
         default: regOut <= 4'b1111; 
     endcase
-        end
-        else begin
-            regOut <= 4'b1111; 
-        end
-    end
 endmodule
 
 //testbench
 module decoder_tb();
-    reg enable;
     reg [1:0] indexIn;
     wire [3:0] regOut;
 
     decoder dec0(
-        .en(enable),
         .index(indexIn),
-        .regOut(regOut));
+        .regOut(regOut)
+    );
     
     initial begin
-        enable = 0;
         indexIn = 2'b00;
         #5
-        enable = 1;
-        #5
         indexIn = 2'b01;
         #5
         indexIn = 2'b10;

lab2CA.srcs/sources_1/new/CPU9bits.v

@@ -2,12 +2,13 @@
 
 module CPU9bits(
     input wire reset, clk,
+    output reg [8:0] result,
     output wire done
     );
 
     wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N, bankData, bankOP,jumpNeg;
-    wire [2:0] FU;
     wire [3:0] aluOp;
+    wire [2:0] FU;
     wire [1:0] bankS;
     wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link, js, dataMemEn;
 
@@ -27,7 +28,6 @@ module CPU9bits(
     RegFile RF(
         .clk(clk),
         .reset(reset),
-        .enable(RegEn),
         .write_index(instr[4:3]),
         .op0_idx(instr[4:3]),
         .op1_idx(instr[2:1]),
@@ -39,7 +39,6 @@ module CPU9bits(
     RegFile Bank(
         .clk(clk),
         .reset(reset),
-        .enable(bankS[1]),
         .write_index(instr[2:1]),
         .op0_idx(instr[2:1]),
         .op1_idx(2'b00),//Doesn't matter
@@ -176,6 +175,31 @@ module CPU9bits(
         .switch(link)
     );
 
+    always @ (instr, op0, op1)
+    begin
+        case(instr[8:5])
+        4'b0001: // Load Byte
+            result <= dataMemOut;
+        4'b0011: // Link
+            result <= linkData;
+        4'b0101: // Add/Subtract
+            result <= AluOut;
+        4'b0110: // Add Immediate
+            result <= AddiOut;
+        4'b0111: // Set if Less Than
+            result <= AluOut;
+        4'b1010: // Bank Load/Bank Store
+            result <= RFIn;
+        4'b1101: // NOR
+            result <= AluOut;
+        4'b1110: // OR/AND
+            result <= AluOut;
+        4'b1111: // Shift Right Logical/Shift Left Logical
+            result <= AluOut;
+        default:
+            result <= 9'bXXXXXXXXX;
+        endcase
+    end
 
 endmodule
 

lab2CA.srcs/sources_1/new/RegFile.v

@@ -1,6 +1,6 @@
 `timescale 1ns / 1ps
 
-module RegFile(input wire clk, reset, enable,
+module RegFile(input wire clk, reset,
                 input wire [1:0] write_index, op0_idx, op1_idx,
                 input wire [8:0] write_data,
                 output wire [8:0] op0, op1);
@@ -11,7 +11,6 @@ module RegFile(input wire clk, reset, enable,
     // To select a register En input must be 2'b00
     
     decoder d0(
-        .en(enable),
         .index(write_index),
         .regOut(decOut)
     );
@@ -67,7 +66,7 @@ endmodule
 module regFile_tb();
     reg [8:0] write_d;
     reg [1:0] w_idx, op0_idx, op1_idx;
-    reg reset,clk, enable;
+    reg reset,clk;
     wire [8:0] op0,op1;
 
     initial begin
@@ -79,7 +78,6 @@ module regFile_tb();
 
     RegFile regFile0(
         .clk(clk),
-        .enable(enable),
         .reset(reset),
         .write_index(w_idx),
         .op0_idx(op0_idx),
@@ -94,7 +92,6 @@ module regFile_tb();
         reset = 1;
         #5
         reset = 0;
-        enable = 1;
         w_idx = 2'b00;
         op0_idx = 2'b00;
         op1_idx = 2'b00;