Minor adjustments
This commit is contained in:
@@ -263,7 +263,7 @@ module decoder (
|
||||
input wire En,
|
||||
output reg [3:0] regOut);
|
||||
|
||||
always @ (index)
|
||||
always @ (index, En)
|
||||
if (En == 0) begin
|
||||
case(index)
|
||||
2'b00: regOut <= 4'b1110;
|
||||
|
||||
Reference in New Issue
Block a user