Minor adjustments

2019-04-10 12:52:42 -04:00
parent a1887d7baf
commit b1f1a7339b
4 changed files with 6 additions and 7 deletions
--- a/lab2CA.srcs/sources_1/new/CPU9bits.v
+++ b/lab2CA.srcs/sources_1/new/CPU9bits.v
@@ -4,8 +4,7 @@ module CPU9bits(
    input wire reset, clk,
    output wire [8:0] result,
    output wire done
-    );
-
+        );
    
    wire [8:0] RFIn,FUAddr;
    wire [1:0] instr;
@@ -85,7 +84,7 @@ module CPU9bits_tb();
    	reset = 1'b1;
    	#10
    	reset = 1'b0;
-    	#50
+    	#50000
        $finish;
        
    end