Minor adjustments

2019-04-10 12:52:42 -04:00
parent a1887d7baf
commit b1f1a7339b
4 changed files with 6 additions and 7 deletions
--- a/lab2CA.srcs/sources_1/new/ControlUnit.v
+++ b/lab2CA.srcs/sources_1/new/ControlUnit.v
@@ -6,7 +6,8 @@ module ControlUnit(
    output reg [3:0] aluOut,
    output reg [2:0] FU,
    output reg [1:0] bank,
-    output reg addi, mem, dataMemEn, RegEn, halt, link, js);
+    output reg addi, mem, dataMemEn, RegEn, halt, link, js
+        );
    
    always @(instIn, functBit)
    begin