Minor adjustments

lab2CA.srcs/sources_1/new/FetchUnit.v

@@ -1,9 +1,8 @@
 `timescale 1ns / 1ps
 
 module FetchUnit(
-    input wire clk, reset, 
-    input wire op_idx,
     input wire [8:0] AddrIn,
+    input wire clk, reset, op_idx,
     output wire [8:0] AddrOut
         );