Minor adjustments

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -263,7 +263,7 @@ module decoder (
     input wire En,
     output reg [3:0] regOut);
     
-    always @ (index)
+    always @ (index, En)
     if (En == 0) begin
         case(index) 
             2'b00: regOut <= 4'b1110; 

lab2CA.srcs/sources_1/new/CPU9bits.v

@@ -6,7 +6,6 @@ module CPU9bits(
     output wire done
         );
     
-    
     wire [8:0] RFIn,FUAddr;
     wire [1:0] instr;
     wire fetchBranch, RegEn;
@@ -85,7 +84,7 @@ module CPU9bits_tb();
     	reset = 1'b1;
     	#10
     	reset = 1'b0;
-    	#50
+    	#50000
         $finish;
         
     end

lab2CA.srcs/sources_1/new/ControlUnit.v

@@ -6,7 +6,8 @@ module ControlUnit(
     output reg [3:0] aluOut,
     output reg [2:0] FU,
     output reg [1:0] bank,
-    output reg addi, mem, dataMemEn, RegEn, halt, link, js);
+    output reg addi, mem, dataMemEn, RegEn, halt, link, js
+        );
     
     always @(instIn, functBit)
     begin

lab2CA.srcs/sources_1/new/FetchUnit.v

@@ -1,9 +1,8 @@
 `timescale 1ns / 1ps
 
 module FetchUnit(
-    input wire clk, reset, 
-    input wire op_idx,
     input wire [8:0] AddrIn,
+    input wire clk, reset, op_idx,
     output wire [8:0] AddrOut
         );