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Renamed some things; adder is now implemented in ALU

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WilliamMiceli
2019-02-15 17:09:44 -05:00
parent d6cee0483c
commit b2dfc05db8
1 changed files with 14 additions and 9 deletions
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23
lab2CA.srcs/sources_1/new/ALU.v
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@@ -8,9 +8,14 @@ module ALU(
); );
// Wires for connecting the modules to the mux // Wires for connecting the modules to the mux
wire [8:0] A,B,C,D,E,F,G,H; wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H;
// A (000) - Add // A (000) - Add
adder_9bit(
.A(operand0),
.B(operand1),
.Cin(1'b0),
.Sum(result_A));
// B (001) - Subtract // B (001) - Subtract
// C (010) - OR // C (010) - OR
// D (011) - NOR // D (011) - NOR
@@ -23,14 +28,14 @@ module ALU(
// MUX chooses which result to show based on the OPCODE // MUX chooses which result to show based on the OPCODE
mux_8_1 mux_result( mux_8_1 mux_result(
.switch(opcode), .switch(opcode),
.A(A), .A(result_A),
.B(B), .B(result_B),
.C(C), .C(result_C),
.D(D), .D(result_D),
.E(E), .E(result_E),
.F(F), .F(result_F),
.G(G), .G(result_G),
.H(H), .H(result_H),
.out(result)); .out(result));
endmodule endmodule