Reverting removing the enable signals to test if that is the issue

lab2CA.srcs/sources_1/new/RegFile.v

@@ -1,6 +1,6 @@
 `timescale 1ns / 1ps
 
-module RegFile(input wire clk, reset,
+module RegFile(input wire clk, reset, enable,
                 input wire [1:0] write_index, op0_idx, op1_idx,
                 input wire [8:0] write_data,
                 output wire [8:0] op0, op1);
@@ -11,6 +11,7 @@ module RegFile(input wire clk, reset,
     // To select a register En input must be 2'b00
     
     decoder d0(
+        .en(enable),
         .index(write_index),
         .regOut(decOut)
     );
@@ -66,7 +67,7 @@ endmodule
 module regFile_tb();
     reg [8:0] write_d;
     reg [1:0] w_idx, op0_idx, op1_idx;
-    reg reset,clk;
+    reg reset,clk, enable;
     wire [8:0] op0,op1;
 
     initial begin
@@ -78,6 +79,7 @@ module regFile_tb();
 
     RegFile regFile0(
         .clk(clk),
+        .enable(enable),
         .reset(reset),
         .write_index(w_idx),
         .op0_idx(op0_idx),
@@ -92,6 +94,7 @@ module regFile_tb();
         reset = 1;
         #5
         reset = 0;
+        enable = 1;
         w_idx = 2'b00;
         op0_idx = 2'b00;
         op1_idx = 2'b00;