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Reverting removing the enable signals to test if that is the issue

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WilliamMiceli
2019-04-06 14:15:51 -04:00
parent 443d01eba1
commit b4f855c65b
2 changed files with 26 additions and 12 deletions
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31
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -259,32 +259,43 @@ module comparator_tb();
endmodule endmodule
module decoder ( module decoder (
input wire en,
input wire [1:0] index, input wire [1:0] index,
output reg [3:0] regOut); output reg [3:0] regOut);
always @ (index) always @(en, index)begin
case(index) if(en == 0)begin
2'b00: regOut <= 4'b1110; case(index)
2'b01: regOut <= 4'b1101; 2'b00: regOut <= 4'b1110;
2'b10: regOut <= 4'b1011; 2'b01: regOut <= 4'b1101;
2'b11: regOut <= 4'b0111; 2'b10: regOut <= 4'b1011;
default: regOut <= 4'b1111; 2'b11: regOut <= 4'b0111;
endcase default: regOut <= 4'b1111;
endcase
end
else begin
regOut <= 4'b1111;
end
end
endmodule endmodule
//testbench //testbench
module decoder_tb(); module decoder_tb();
reg enable;
reg [1:0] indexIn; reg [1:0] indexIn;
wire [3:0] regOut; wire [3:0] regOut;
decoder dec0( decoder dec0(
.en(enable),
.index(indexIn), .index(indexIn),
.regOut(regOut) .regOut(regOut));
);
initial begin initial begin
enable = 0;
indexIn = 2'b00; indexIn = 2'b00;
#5 #5
enable = 1;
#5
indexIn = 2'b01; indexIn = 2'b01;
#5 #5
indexIn = 2'b10; indexIn = 2'b10;

7
lab2CA.srcs/sources_1/new/RegFile.v
View File

@@ -1,6 +1,6 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
module RegFile(input wire clk, reset, module RegFile(input wire clk, reset, enable,
input wire [1:0] write_index, op0_idx, op1_idx, input wire [1:0] write_index, op0_idx, op1_idx,
input wire [8:0] write_data, input wire [8:0] write_data,
output wire [8:0] op0, op1); output wire [8:0] op0, op1);
@@ -11,6 +11,7 @@ module RegFile(input wire clk, reset,
// To select a register En input must be 2'b00 // To select a register En input must be 2'b00
decoder d0( decoder d0(
.en(enable),
.index(write_index), .index(write_index),
.regOut(decOut) .regOut(decOut)
); );
@@ -66,7 +67,7 @@ endmodule
module regFile_tb(); module regFile_tb();
reg [8:0] write_d; reg [8:0] write_d;
reg [1:0] w_idx, op0_idx, op1_idx; reg [1:0] w_idx, op0_idx, op1_idx;
reg reset,clk; reg reset,clk, enable;
wire [8:0] op0,op1; wire [8:0] op0,op1;
initial begin initial begin
@@ -78,6 +79,7 @@ module regFile_tb();
RegFile regFile0( RegFile regFile0(
.clk(clk), .clk(clk),
.enable(enable),
.reset(reset), .reset(reset),
.write_index(w_idx), .write_index(w_idx),
.op0_idx(op0_idx), .op0_idx(op0_idx),
@@ -92,6 +94,7 @@ module regFile_tb();
reset = 1; reset = 1;
#5 #5
reset = 0; reset = 0;
enable = 1;
w_idx = 2'b00; w_idx = 2'b00;
op0_idx = 2'b00; op0_idx = 2'b00;
op1_idx = 2'b00; op1_idx = 2'b00;