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Added bank to CPU9bits

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This commit is contained in:
jose.rodriguezlabra
2019-03-24 12:11:12 -04:00
parent 191ca46f2d
commit bab680ea27
59 changed files with 629 additions and 2560 deletions
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38
lab2CA.srcs/sources_1/new/CPU9bits.v
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@@ -5,9 +5,10 @@ module CPU9bits(
output wire done
);
wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N;
wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N, bankData, bankOP;
wire [2:0] FU;
wire [3:0] aluOp;
wire [1:0] bankS;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link;
instructionMemory iM(
@@ -36,6 +37,18 @@ module CPU9bits(
.op1(op1)
);
RegFile Bank(
.clk(clk),
.reset(reset),
.enable(bankS[1]),
.write_index(instr[2:1]),
.op0_idx(instr[2:1]),
.op1_idx(2'b00),//Doesn't matter
.write_data(op0),
.op0(bankOP),
.op1()
);
FetchUnit FetchU(
.clk(clk),
.reset(reset),
@@ -60,7 +73,8 @@ module CPU9bits(
.mem(loadS),
.RegEn(RegEn),
.halt(done),
.link(link)
.link(link),
.bank(bankS)
);
@@ -85,11 +99,11 @@ module CPU9bits(
.out(JBRes),
.switch(FU[2]));
sign_extend_2bit SE1(
sign_extend_3bit SE1(
.A(instr[2:0]),
.B(SE1N));
sign_extend_4bit SE2(
sign_extend_5bit SE2(
.A(instr[4:0]),
.B(SE2N));
@@ -108,7 +122,7 @@ module CPU9bits(
.Sum(AddiOut),
.Cout(cout1));
sign_extend_2bit SE3(
sign_extend_3bit SE3(
.A(instr[2:0]),
.B(SE3N));
@@ -123,13 +137,21 @@ module CPU9bits(
mux_2_1 mux4(
.A(linkData),
.B(9'b000000001), // This is DATA MEM
.out(RFIn),
.B(dataMemOut), // This is DATA MEM
.out(bankData),
.switch(loadS));
///--------------------------Bank stuff
mux_2_1 mux5(
.A(bankData),
.B(bankOP),
.out(RFIn),
.switch(bankS[0]));
///--------------------------Link Stuff
mux_2_1 mux5(
mux_2_1 mux6(
.A(loadMux),
.B(PCout),
.out(linkData),

35
lab2CA.srcs/sources_1/new/ControlUnit.v
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@@ -9,7 +9,8 @@ module ControlUnit(
output reg mem,
output reg RegEn,
output reg halt,
output reg link);
output reg link,
output reg [1:0] bank);
always @(instIn, functBit)begin
case(instIn)
@@ -22,6 +23,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
else begin
aluOut <= 4'b0000; //Add
@@ -31,6 +33,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b1101: begin
aluOut <= 4'b0011; //nor
@@ -40,6 +43,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b0100: begin
aluOut <= 4'b1011; //zero
@@ -49,6 +53,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b1110:
if(functBit == 1) begin
@@ -59,6 +64,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
else begin
aluOut <= 4'b0010; //or
@@ -68,6 +74,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b1111:
if(functBit == 1) begin
@@ -78,6 +85,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
else begin
aluOut <= 4'b0101; //shift left
@@ -87,6 +95,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b0111: begin
aluOut <= 4'b1001; //Less than
@@ -96,15 +105,17 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b0110: begin
aluOut <= 4'b0000;
addi <= 1'b1; // addi
RegEn <= 1'b1;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b1001: begin
aluOut <= 4'b0000;
@@ -114,6 +125,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b0011: begin // link
halt <= 1'b0;
@@ -123,6 +135,7 @@ module ControlUnit(
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b1;
bank <= 2'b10;
end
4'b1100: begin
aluOut <= 4'b0000;
@@ -132,6 +145,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b1000: begin
aluOut <= 4'b0000;
@@ -141,6 +155,7 @@ module ControlUnit(
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b0001: begin
aluOut <= 4'b0000;
@@ -150,6 +165,7 @@ module ControlUnit(
addi <= 1'b0;
halt <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b0010: begin
aluOut <= 4'b0000;
@@ -159,8 +175,19 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
4'b0000: begin // regs should initialize at 0, so we shouldn't need to declare it everywhere
4'b1010: begin
halt <= 1'b0; // bank
RegEn <= !functBit;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= {functBit,functBit};
end
4'b0000: begin
halt <= 1'b1; // halt
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
@@ -168,6 +195,7 @@ module ControlUnit(
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
default: begin
halt <= 1'b1;
@@ -177,6 +205,7 @@ module ControlUnit(
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
end
endcase
end

2
lab2CA.srcs/sources_1/new/dataMemory.v
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@@ -27,7 +27,7 @@ module dataMemory(
memory[15] <= 9'b000000000;
end
always@(address)begin
always@(address, clk, memory)begin
if(clk == 1'b1)begin
readData <= memory[address];
if(writeEnable == 1'b0)begin

19
lab2CA.srcs/sources_1/new/instructionMemory.v
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@@ -25,16 +25,25 @@ module instructionMemory(
memory[10] <= 9'b111011000; //or
memory[11] <= 9'b111011001; //and
memory[12] <= 9'b111111000; //sll
memory[13] <= 9'b111111001; //srl
//memory[13] <= 9'b111111001; //srl
//------------------------------
memory[13] <= 9'b010000000; //zero
memory[14] <= 9'b011000011; //addi
memory[15] <= 9'b101000000; //banks
memory[16] <= 9'b010000000; //zero
memory[17] <= 9'b101000001; //bankl
memory[18] <= 9'b010000000; //zero
memory[19] <= 9'b101000000; //banks
// memory[14] <= 9'b100100010; //j
memory[14] <= 9'b010001000; //zero
memory[15] <= 9'b110001101; //beq
memory[16] <= 9'b100001000; //jr
//memory[18] <= 9'b010001000; //zero
//memory[19] <= 9'b110001101; //beq
//memory[20] <= 9'b100001000; //jr
memory[17] <= 9'b100111100; //j
//memory[17] <= 9'b100111100; //j
memory[20] <= 9'b000000000;
end