Added bank to CPU9bits

2019-03-24 12:11:12 -04:00
parent 191ca46f2d
commit bab680ea27
59 changed files with 629 additions and 2560 deletions
--- a/lab2CA.srcs/sources_1/new/dataMemory.v
+++ b/lab2CA.srcs/sources_1/new/dataMemory.v
@@ -27,7 +27,7 @@ module dataMemory(
        memory[15] <= 9'b000000000;
    end

-    always@(address)begin
+    always@(address, clk, memory)begin
        if(clk == 1'b1)begin
        readData <= memory[address];
        if(writeEnable == 1'b0)begin