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This commit is contained in:
Johannes
2019-04-11 18:36:00 -04:00
parent 42d2bf2d80
commit bc9c02322c
12 changed files with 367 additions and 277 deletions
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83
lab2CA.srcs/sources_1/new/CPU9bits.v
View File

@@ -6,13 +6,16 @@ module CPU9bits(
output wire done
);
wire [8:0] RFIn,FUAddr;
wire [1:0] instr;
wire fetchBranch, RegEn;
wire [50:0] FDOut, FDPipOut;
wire [8:0] RFIn,FUAddr, op0_ext, op1_ext, wr_ext, op0_sub, op1_sub, op0_zero, op1_zero, op0_and, op1_and, newOp0, newOp1;
wire [1:0] instr, op0_idx, op1_idx;
wire fetchBranch, RegEn, compare0, compare1;
wire [50:0] FDOut, FDPipOut, EMIn;
wire [61:0] EMOut, EMPipOut;
assign result = RFIn;
assign EMIn = {FDPipOut[50:42], newOp0, newOp1, FDPipOut[23:0]};
FDModule FD(
.reset(reset),
@@ -23,7 +26,11 @@ module CPU9bits(
.AddrIn(FUAddr),
.RFIdx(instr),
.result(FDOut),
.done(done)
.done(done),
.compare0(compare0),
.compare1(compare1),
.op0_idx(op0_idx),
.op1_idx(op1_idx)
);
fDPipReg pipe1(
@@ -37,7 +44,7 @@ module CPU9bits(
EMModule EM(
.reset(reset),
.clk(clk),
.PipIn(FDPipOut),
.PipIn(EMIn),
.PipOut(EMOut)
);
@@ -57,6 +64,70 @@ module CPU9bits(
.fetchBranch(fetchBranch),
.RegEn(RegEn)
);
sign_extend_2bit ext0(
.A(op0_idx),
.B(op0_ext)
);
sign_extend_2bit ext1(
.A(op1_idx),
.B(op1_ext)
);
sign_extend_2bit ext2(
.A(instr),
.B(wr_ext)
);
sub_9bit sub0(
.A(op0_ext),
.B(wr_ext),
.C(op0_sub)
);
sub_9bit sub1(
.A(op1_ext),
.B(wr_ext),
.C(op1_sub)
);
BEQ beq0(
.A(op0_sub),
.B(op0_zero)
);
BEQ beq1(
.A(op1_sub),
.B(op1_zero)
);
and_9bit and0(
.A(~op0_zero),
.B({8'b00000000,compare0}),
.C(op0_and)
);
and_9bit and1(
.A(~op1_zero),
.B({8'b00000000,compare1}),
.C(op1_and)
);
mux_2_1 mux0(
.switch(op0_and[0]),
.A(FDOut[41:33]),
.B(EMPipOut[33:25]), //ALUOut
.out(newOp0)
);
mux_2_1 mux1(
.switch(op1_and[0]),
.A(FDOut[32:24]),
.B(EMPipOut[33:25]), //ALUOut
.out(newOp1)
);
endmodule

49
lab2CA.srcs/sources_1/new/ControlUnit.v
View File

@@ -6,15 +6,24 @@ module ControlUnit(
output reg [3:0] aluOut,
output reg [2:0] FU,
output reg [1:0] bank,
<<<<<<< Updated upstream
output reg addi, mem, dataMemEn, RegEn, halt, link, js
);
=======
output reg addi, mem, dataMemEn, RegEn, halt, link, js, compare0, compare1
);
>>>>>>> Stashed changes
always @(instIn, functBit)
begin
case(instIn)
4'b0000: // Halt/NOP
begin
<<<<<<< Updated upstream
halt <= functBit;
=======
halt <= ~functBit;
>>>>>>> Stashed changes
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
@@ -24,6 +33,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b0;
compare1 <= 1'b0;
end
4'b0001: // Load Byte
begin
@@ -37,6 +48,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
4'b0010: // Store Byte
begin
@@ -50,6 +63,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
4'b0011: // Link
begin
@@ -63,6 +78,8 @@ module ControlUnit(
link <= 1'b1;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b0;
compare1 <= 1'b0;
end
4'b0100: // Zero
begin
@@ -76,6 +93,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b0;
compare1 <= 1'b0;
end
4'b0101: // Add/Subtract
if(functBit == 1) // Subtract
@@ -90,6 +109,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
else // Add
begin
@@ -103,6 +124,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
4'b0110: // Add Immediate
begin
@@ -116,6 +139,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b0;
end
4'b0111: // Set if Less Than
begin
@@ -129,6 +154,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
4'b1000: // Jump to Register
begin
@@ -142,6 +169,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b0;
end
4'b1001: // Jump Forward
begin
@@ -155,6 +184,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b0;
compare1 <= 1'b0;
end
4'b1010: // Bank Load/Bank Store
begin
@@ -168,6 +199,8 @@ module ControlUnit(
link <= 1'b0;
bank <= {functBit,functBit};
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b0;
end
4'b1011: // Jump Backward
begin
@@ -181,6 +214,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b1;
compare0 <= 1'b0;
compare1 <= 1'b0;
end
4'b1100: // Branch if Zero
begin
@@ -194,6 +229,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b0;
end
4'b1101: // NOR
begin
@@ -207,6 +244,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
4'b1110: // OR/AND
if(functBit == 1) // AND
@@ -221,6 +260,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
else // OR
begin
@@ -234,6 +275,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
4'b1111: // Shift Right Logical/Shift Left Logical
if(functBit == 1) // Shift Right Logical
@@ -248,6 +291,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
else // Shift Left Logical
begin
@@ -261,6 +306,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b1;
compare1 <= 1'b1;
end
default:
begin
@@ -274,6 +321,8 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
compare0 <= 1'b0;
compare1 <= 1'b0;
end
endcase
end

11
lab2CA.srcs/sources_1/new/FDModule.v
View File

@@ -4,8 +4,9 @@ module FDModule(
input wire reset, clk, FUIdx, En,
input wire [8:0] RFIn, AddrIn,
input wire[1:0] RFIdx,
output wire [1:0] op0_idx, op1_idx,
output wire [50:0] result,
output wire done
output wire done, compare0, compare1
);
@@ -13,9 +14,11 @@ module FDModule(
wire [3:0] aluOp;
wire [2:0] FU;
wire [1:0] bankS;
wire addiS, RegEn, loadS, halt, link, js, dataMemEn;
wire addiS, RegEn, loadS, halt, link, js, dataMemEn ;
assign result = {instr,op0,op1,PCout,addiS,RegEn,loadS,link,js,dataMemEn,aluOp,FU,bankS}; // concat all signals into one
assign op0_idx = instr[4:3];
assign op1_idx = instr[2:1];
instructionMemory iM(
@@ -55,6 +58,8 @@ module FDModule(
.halt(done),
.link(link),
.bank(bankS),
.js(js)
.js(js),
.compare0(compare0),
.compare1(compare1)
);
endmodule