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Just changes made for simulations

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This commit is contained in:
Johannes
2019-03-24 18:55:49 -04:00
parent 033e606d5d
commit be06f4e457
73 changed files with 1642 additions and 3006 deletions
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19
lab2CA.runs/synth_1/gen_run.xml
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@@ -1,11 +1,14 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1553093608">
<File Type="PA-TCL" Name="CPU9bits.tcl"/>
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
<File Type="RDS-RDS" Name="CPU9bits.vds"/>
<File Type="RDS-DCP" Name="CPU9bits.dcp"/>
<File Type="RDS-UTIL" Name="CPU9bits_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="CPU9bits_utilization_synth.pb"/>
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1553466509">
<File Type="PA-TCL" Name="CPU9bits_tb.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="CPU9bits_tb_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="CPU9bits_tb_reports.tcl"/>
<File Type="RDS-RDS" Name="CPU9bits_tb.vds"/>
<File Type="RDS-UTIL" Name="CPU9bits_tb_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="CPU9bits_tb_utilization_synth.pb"/>
<File Type="RDS-DCP" Name="CPU9bits_tb.dcp"/>
<File Type="VDS-TIMINGSUMMARY" Name="CPU9bits_tb_timing_summary_synth.rpt"/>
<File Type="VDS-TIMING-PB" Name="CPU9bits_tb_timing_summary_synth.pb"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/ALU.v">
@@ -74,7 +77,7 @@
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="CPU9bits"/>
<Option Name="TopModule" Val="CPU9bits_tb"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">