William/WMU-ECE-3570-Lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
121 Commits 1 Branch 0 Tags
be06f4e4578f26be260963500d1ef2d794ceba4e
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Johannes be06f4e457 Just changes made for simulations
2019-03-24 18:55:49 -04:00
lab2CA.cache/wt
Just changes made for simulations
2019-03-24 18:55:49 -04:00
lab2CA.ip_user_files
fetch unit
2019-02-15 11:20:14 -05:00
lab2CA.runs
Just changes made for simulations
2019-03-24 18:55:49 -04:00
lab2CA.sim/sim_1
Just changes made for simulations
2019-03-24 18:55:49 -04:00
lab2CA.srcs/sources_1
Just changes made for simulations
2019-03-24 18:55:49 -04:00
.gitignore
Excluded Markdown files
2019-02-21 15:11:10 -05:00
Bank_behav1.wcfg
Just changes made for simulations
2019-03-24 18:55:49 -04:00
CPU9bits_tb_behav.wcfg
BEQ and LD fix
2019-03-24 16:05:16 -04:00
lab2CA.xpr
Just changes made for simulations
2019-03-24 18:55:49 -04:00
README.md
Updated README
2019-03-12 21:53:50 -04:00
regFile_tb_behav.wcfg
Better Sim
2019-03-14 14:37:58 -04:00
StringCompare.wcfg
String Compare Working
2019-03-24 17:05:09 -04:00
vivado_10872.backup.jou
stuff
2019-02-16 12:37:12 -05:00
vivado_15076.backup.jou
new thing
2019-02-16 13:04:06 -05:00
vivado_15356.backup.jou
more stuff
2019-02-16 12:42:09 -05:00
vivado.jou
new thing
2019-02-16 13:04:06 -05:00

README.md

ECE 3570 Lab

Unknown Status of Fixes

  • Only two registers are being written to, first two within simulation is not being written to
Reference in New Issue View Git Blame Copy Permalink
Description
No description provided
Readme 5.2 MiB
Languages
C 33.3%
Verilog 26.9%
PureBasic 23.7%
Tcl 16.1%