William/WMU-ECE-3570-Lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

metadat

Browse Source
This commit is contained in:
jose.rodriguezlabra
2019-04-12 00:02:54 -04:00
parent ddf47c7eee
commit bf57055518
34 changed files with 569 additions and 994 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
lab2CA.runs/impl_1/CPU9bits.tcl
View File

@@ -68,7 +68,6 @@ start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-3864-DESKTOP-8QFGS52/incrSyn
create_project -in_memory -part xc7k160tifbg484-2L
set_property design_mode GateLvl [current_fileset]
set_param project.singleFileAddWarning.threshold 0