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This commit is contained in:
jose.rodriguezlabra
2019-04-12 00:02:54 -04:00
parent ddf47c7eee
commit bf57055518
34 changed files with 569 additions and 994 deletions
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71
lab2CA.cache/wt/webtalk_pa.xml
View File

@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Thu Apr 11 21:13:26 2019">
<application name="pa" timeStamp="Fri Apr 12 00:01:49 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="3e90d71c8f614f9191c5fa413d1d835d" type="ProjectID"/>
<property name="ProjectIteration" value="2" type="ProjectIteration"/>
@@ -17,45 +17,68 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="CloseProject" value="3" type="JavaHandler"/>
<property name="CloseProject" value="4" type="JavaHandler"/>
<property name="OpenProject" value="1" type="JavaHandler"/>
<property name="RunImplementation" value="1" type="JavaHandler"/>
<property name="RunSchematic" value="1" type="JavaHandler"/>
<property name="SimulationRelaunch" value="10" type="JavaHandler"/>
<property name="SimulationRun" value="2" type="JavaHandler"/>
<property name="RunSchematic" value="9" type="JavaHandler"/>
<property name="SaveFileProxyHandler" value="1" type="JavaHandler"/>
<property name="SimulationRelaunch" value="26" type="JavaHandler"/>
<property name="SimulationRun" value="3" type="JavaHandler"/>
<property name="ViewTaskImplementation" value="1" type="JavaHandler"/>
<property name="ViewTaskRTLAnalysis" value="1" type="JavaHandler"/>
<property name="ViewTaskRTLAnalysis" value="2" type="JavaHandler"/>
<property name="WaveformSaveConfiguration" value="18" type="JavaHandler"/>
<property name="ZoomIn" value="2" type="JavaHandler"/>
<property name="ZoomOut" value="1" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="BaseDialog_OK" value="5" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="7" type="GuiHandlerData"/>
<property name="BaseDialog_YES" value="1" type="GuiHandlerData"/>
<property name="ClosePlanner_YES" value="1" type="GuiHandlerData"/>
<property name="CodeView_TOGGLE_COLUMN_SELECTION_MODE" value="2" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="36" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="8" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="69" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="21" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="5" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="17" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="5" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="5" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RELAUNCH" value="11" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="2" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="8" type="GuiHandlerData"/>
<property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_DESIGN_HUBS" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="10" type="GuiHandlerData"/>
<property name="MainMenuMgr_FLOW" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_HELP" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORTS" value="5" type="GuiHandlerData"/>
<property name="MainMenuMgr_RUN" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_VIEW" value="8" type="GuiHandlerData"/>
<property name="MainMenuMgr_WINDOW" value="4" type="GuiHandlerData"/>
<property name="MainWinMenuMgr_LAYOUT" value="4" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="14" type="GuiHandlerData"/>
<property name="MsgView_INFORMATION_MESSAGES" value="1" type="GuiHandlerData"/>
<property name="NetlistSchMenuAndMouse_VIEW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RELAUNCH" value="27" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_IN" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_OUT" value="1" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="1" type="GuiHandlerData"/>
<property name="PAViews_DEVICE" value="2" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="3" type="GuiHandlerData"/>
<property name="PAViews_SCHEMATIC" value="1" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="6" type="GuiHandlerData"/>
<property name="PAViews_SCHEMATIC" value="5" type="GuiHandlerData"/>
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
<property name="RDICommands_SAVE_FILE" value="7" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="83" type="GuiHandlerData"/>
<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="5" type="GuiHandlerData"/>
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="30" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="2" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="123" type="GuiHandlerData"/>
<property name="ProjectTab_RELOAD" value="5" type="GuiHandlerData"/>
<property name="RDICommands_SAVE_FILE" value="12" type="GuiHandlerData"/>
<property name="RDICommands_WAVEFORM_SAVE_CONFIGURATION" value="14" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="238" type="GuiHandlerData"/>
<property name="SchMenuAndMouse_EXPAND_CONE" value="1" type="GuiHandlerData"/>
<property name="SelectMenu_HIGHLIGHT" value="1" type="GuiHandlerData"/>
<property name="SelectMenu_MARK" value="1" type="GuiHandlerData"/>
<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="14" type="GuiHandlerData"/>
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="59" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="3" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="222" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="49" type="GuiMode"/>

11
lab2CA.runs/.jobs/vrs_config_74.xml Normal file
View File

@@ -0,0 +1,11 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

1
lab2CA.runs/impl_1/CPU9bits.tcl
View File

@@ -68,7 +68,6 @@ start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-3864-DESKTOP-8QFGS52/incrSyn
create_project -in_memory -part xc7k160tifbg484-2L
set_property design_mode GateLvl [current_fileset]
set_param project.singleFileAddWarning.threshold 0

275
lab2CA.runs/impl_1/CPU9bits.vdi
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@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Thu Apr 11 18:41:54 2019
# Process ID: 10352
# Start of session at: Thu Apr 11 19:41:06 2019
# Process ID: 12740
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits.vdi
@@ -13,18 +13,19 @@ source CPU9bits.tcl -notrace
Command: link_design -top CPU9bits -part xc7k160tifbg484-2L
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
INFO: [Project 1-570] Preparing netlist for logic optimization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 578.137 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 578.020 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
A total of 9 instances were transformed.
RAM16X1S => RAM32X1S (RAMS32): 9 instances
6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:16 . Memory (MB): peak = 583.707 ; gain = 330.434
link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:16 . Memory (MB): peak = 578.020 ; gain = 322.695
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
@@ -35,53 +36,53 @@ INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.787 . Memory (MB): peak = 596.723 ; gain = 13.016
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.703 . Memory (MB): peak = 595.879 ; gain = 17.859
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1b0ead489
Ending Cache Timing Information Task | Checksum: 4fc30cd6
Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1152.047 ; gain = 555.324
Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1165.043 ; gain = 569.164
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1075be1b4
Phase 1 Retarget | Checksum: 43f14207
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.123 . Memory (MB): peak = 1249.324 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 13 cells
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1261.125 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 1 cells and removed 1 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 1075be1b4
Phase 2 Constant propagation | Checksum: 43f14207
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.131 . Memory (MB): peak = 1249.324 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1261.125 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 1075be1b4
Phase 3 Sweep | Checksum: 43f14207
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.151 . Memory (MB): peak = 1249.324 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1261.125 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 1075be1b4
Phase 4 BUFG optimization | Checksum: 43f14207
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.163 . Memory (MB): peak = 1249.324 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1261.125 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 1075be1b4
Phase 5 Shift Register Optimization | Checksum: 9334b39a
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.217 . Memory (MB): peak = 1249.324 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.088 . Memory (MB): peak = 1261.125 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 1075be1b4
Phase 6 Post Processing Netlist | Checksum: 9334b39a
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.221 . Memory (MB): peak = 1249.324 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.090 . Memory (MB): peak = 1261.125 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
@@ -90,7 +91,7 @@ Opt_design Change Summary
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 13 | 0 |
| Retarget | 1 | 1 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
@@ -102,50 +103,32 @@ Opt_design Change Summary
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1249.324 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 1075be1b4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.125 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 9334b39a
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.226 . Memory (MB): peak = 1249.324 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.093 . Memory (MB): peak = 1261.125 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.000 | TNS=0.000 |
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
Running Vector-less Activity Propagation...
Ending Power Optimization Task | Checksum: 9334b39a
Finished Running Vector-less Activity Propagation
Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 1 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 2
Ending PowerOpt Patch Enables Task | Checksum: 1075be1b4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1362.293 ; gain = 0.000
Ending Power Optimization Task | Checksum: 1075be1b4
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.918 . Memory (MB): peak = 1362.293 ; gain = 112.969
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1261.125 ; gain = 0.000
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1075be1b4
Ending Final Cleanup Task | Checksum: 9334b39a
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.125 ; gain = 0.000
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.293 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 1075be1b4
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.125 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 9334b39a
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.125 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
28 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
22 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1362.293 ; gain = 778.586
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.293 ; gain = 0.000
opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1261.125 ; gain = 683.105
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.125 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_opt.dcp' has been generated.
@@ -174,127 +157,127 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3d9e6472
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.125 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1963521c
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1362.293 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1261.125 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.125 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15f430561
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 184c2c7e6
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1265.020 ; gain = 3.895
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1c86a0072
Phase 1.3 Build Placer Netlist Model | Checksum: 188e0661e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1265.020 ; gain = 3.895
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1c86a0072
Phase 1.4 Constrain Clocks/Macros | Checksum: 188e0661e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 1c86a0072
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1265.020 ; gain = 3.895
Phase 1 Placer Initialization | Checksum: 188e0661e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1265.020 ; gain = 3.895
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1c86a0072
Phase 2.1 Floorplanning | Checksum: 188e0661e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1266.902 ; gain = 5.777
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
Phase 2 Global Placement | Checksum: 2ac705958
Phase 2 Global Placement | Checksum: 2030f88ae
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1275.738 ; gain = 14.613
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 2ac705958
Phase 3.1 Commit Multi Column Macros | Checksum: 2030f88ae
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1275.738 ; gain = 14.613
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1dbfff5a9
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2ac85731a
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1275.738 ; gain = 14.613
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 21cc4f0ec
Phase 3.3 Area Swap Optimization | Checksum: 1d9aac728
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1275.738 ; gain = 14.613
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 21cc4f0ec
Phase 3.4 Pipeline Register Optimization | Checksum: 1d9aac728
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1275.738 ; gain = 14.613
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 206a7ccd0
Phase 3.5 Small Shape Detail Placement | Checksum: 2ad3da515
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 206a7ccd0
Phase 3.6 Re-assign LUT pins | Checksum: 2ad3da515
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 206a7ccd0
Phase 3.7 Pipeline Register Optimization | Checksum: 2ad3da515
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 3 Detail Placement | Checksum: 206a7ccd0
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
Phase 3 Detail Placement | Checksum: 2ad3da515
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: 206a7ccd0
Phase 4.1 Post Commit Optimization | Checksum: 2ad3da515
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 206a7ccd0
Phase 4.2 Post Placement Cleanup | Checksum: 2ad3da515
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 206a7ccd0
Phase 4.3 Placer Reporting | Checksum: 2ad3da515
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 1f13c29b7
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1284.789 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 2a7ff8ccd
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f13c29b7
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2a7ff8ccd
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Ending Placer Task | Checksum: 161b453db
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
Ending Placer Task | Checksum: 1c01f6f47
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
INFO: [Common 17-83] Releasing license: Implementation
45 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
39 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.293 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1284.789 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.117 . Memory (MB): peak = 1362.293 ; gain = 0.000
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.111 . Memory (MB): peak = 1284.789 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file CPU9bits_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1362.293 ; gain = 0.000
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1284.789 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1362.293 ; gain = 0.000
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1284.789 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
@@ -306,68 +289,68 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: b86b4c57 ConstDB: 0 ShapeSum: a9490784 RouteDB: 0
Checksum: PlaceDB: e1291a6d ConstDB: 0 ShapeSum: def654da RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 12dabf8e5
Phase 1 Build RT Design | Checksum: f4f19886
Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1499.332 ; gain = 137.039
Post Restoration Checksum: NetGraph: 45c7ac9c NumContArr: e7e44c49 Constraints: 0 Timing: 0
Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1500.094 ; gain = 215.305
Post Restoration Checksum: NetGraph: 4b3a30b8 NumContArr: a9b767ce Constraints: 0 Timing: 0
Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 12dabf8e5
Phase 2.1 Fix Topology Constraints | Checksum: f4f19886
Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1504.012 ; gain = 141.719
Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1504.246 ; gain = 219.457
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 12dabf8e5
Phase 2.2 Pre Route Cleanup | Checksum: f4f19886
Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1504.012 ; gain = 141.719
Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1504.246 ; gain = 219.457
Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: d6870417
Phase 2 Router Initialization | Checksum: 1793c9dea
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 658f3c2e
Phase 3 Initial Routing | Checksum: 72ce7f92
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 52
Number of Nodes with overlaps = 19
Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: fbcb5761
Phase 4.1 Global Iteration 0 | Checksum: 10c1152b4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Phase 4 Rip-up And Reroute | Checksum: fbcb5761
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Phase 4 Rip-up And Reroute | Checksum: 10c1152b4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: fbcb5761
Phase 5 Delay and Skew Optimization | Checksum: 10c1152b4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: fbcb5761
Phase 6.1 Hold Fix Iter | Checksum: 10c1152b4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Phase 6 Post Hold Fix | Checksum: fbcb5761
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Phase 6 Post Hold Fix | Checksum: 10c1152b4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.0201332 %
Global Horizontal Routing Utilization = 0.0294118 %
Global Vertical Routing Utilization = 0.00697219 %
Global Horizontal Routing Utilization = 0.00971867 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
@@ -377,10 +360,10 @@ Router Utilization Summary
Number of Node Overlaps = 0
Congestion Report
North Dir 1x1 Area, Max Cong = 19.8198%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 18.018%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 29.4118%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 22.0588%, No Congested Regions.
North Dir 1x1 Area, Max Cong = 14.4144%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 14.4144%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 20.5882%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 16.1765%, No Congested Regions.
------------------------------
Reporting congestion hotspots
@@ -402,38 +385,38 @@ Direction: West
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: fbcb5761
Phase 7 Route finalize | Checksum: 10c1152b4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: fbcb5761
Phase 8 Verifying routed nets | Checksum: 10c1152b4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: b44fe7b0
Phase 9 Depositing Routes | Checksum: 10798d720
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
57 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
51 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 1531.199 ; gain = 168.906
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1531.199 ; gain = 0.000
route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:30 . Memory (MB): peak = 1530.906 ; gain = 246.117
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1530.906 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.090 . Memory (MB): peak = 1531.199 ; gain = 0.000
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1530.906 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
Command: report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
@@ -455,7 +438,7 @@ INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
68 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
62 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation
@@ -468,4 +451,4 @@ INFO: [runtcl-4] Executing : report_clock_utilization -file CPU9bits_clock_utili
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Thu Apr 11 18:43:05 2019...
INFO: [Common 17-206] Exiting Vivado at Thu Apr 11 19:42:15 2019...

2
lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:43:05 2019
| Date : Thu Apr 11 19:42:15 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx
| Design : CPU9bits

36
lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:43:05 2019
| Date : Thu Apr 11 19:42:15 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt
| Design : CPU9bits
@@ -44,7 +44,7 @@ Table of Contents
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 164 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG |
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 70 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
@@ -72,7 +72,7 @@ Table of Contents
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 163 | 2800 | 46 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 61 | 2800 | 14 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
@@ -105,7 +105,7 @@ All Modules
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
| g0 | BUFG/O | n/a | | | | 164 | 0 | 0 | 0 | clk_IBUF_BUFG |
| g0 | BUFG/O | n/a | | | | 61 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
@@ -113,25 +113,25 @@ All Modules
**** GT Loads column represents load cell count of GT types
+----+------+----+
| | X0 | X1 |
+----+------+----+
| Y4 | 0 | 0 |
| Y3 | 0 | 0 |
| Y2 | 0 | 0 |
| Y1 | 164 | 0 |
| Y0 | 0 | 0 |
+----+------+----+
+----+-----+----+
| | X0 | X1 |
+----+-----+----+
| Y4 | 0 | 0 |
| Y3 | 0 | 0 |
| Y2 | 0 | 0 |
| Y1 | 61 | 0 |
| Y0 | 0 | 0 |
+----+-----+----+
7. Clock Region Cell Placement per Global Clock: Region X0Y1
------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+---------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+---------------+
| g0 | n/a | BUFG/O | None | 164 | 0 | 163 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+---------------+
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
| g0 | n/a | BUFG/O | None | 61 | 0 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts

37
lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:42:32 2019
| Date : Thu Apr 11 19:41:43 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
| Design : CPU9bits
@@ -23,8 +23,8 @@ Table of Contents
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets | 9 |
| Unused register locations in slices containing registers | 61 |
| Number of unique control sets | 4 |
| Unused register locations in slices containing registers | 27 |
+----------------------------------------------------------+-------+
@@ -34,8 +34,8 @@ Table of Contents
+--------+--------------+
| Fanout | Control Sets |
+--------+--------------+
| 9 | 8 |
| 16+ | 1 |
| 9 | 2 |
| 16+ | 2 |
+--------+--------------+
@@ -45,30 +45,25 @@ Table of Contents
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 0 | 0 |
| No | No | No | 9 | 3 |
| No | No | Yes | 0 | 0 |
| No | Yes | No | 91 | 35 |
| No | Yes | No | 34 | 15 |
| Yes | No | No | 0 | 0 |
| Yes | No | Yes | 0 | 0 |
| Yes | Yes | No | 72 | 23 |
| Yes | Yes | No | 18 | 9 |
+--------------+-----------------------+------------------------+-----------------+--------------+
4. Detailed Control Set Information
-----------------------------------
+----------------+-------------------------+------------------+------------------+----------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+----------------+-------------------------+------------------+------------------+----------------+
| clk_IBUF_BUFG | pipe2/Dout_reg[6]_2[0] | reset_IBUF | 5 | 9 |
| clk_IBUF_BUFG | pipe2/Dout_reg[6]_1[0] | reset_IBUF | 2 | 9 |
| clk_IBUF_BUFG | pipe2/E[0] | reset_IBUF | 2 | 9 |
| clk_IBUF_BUFG | pipe2/Dout_reg[6]_3[0] | reset_IBUF | 4 | 9 |
| clk_IBUF_BUFG | pipe1/Dout_reg[43]_0[0] | reset_IBUF | 2 | 9 |
| clk_IBUF_BUFG | pipe1/Dout_reg[1]_0[0] | reset_IBUF | 2 | 9 |
| clk_IBUF_BUFG | pipe1/Dout_reg[1]_1[0] | reset_IBUF | 2 | 9 |
| clk_IBUF_BUFG | pipe1/E[0] | reset_IBUF | 4 | 9 |
| clk_IBUF_BUFG | | reset_IBUF | 35 | 91 |
+----------------+-------------------------+------------------+------------------+----------------+
+----------------+------------------------+------------------+------------------+----------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+----------------+------------------------+------------------+------------------+----------------+
| clk_IBUF_BUFG | pipe2/Dout_reg[5]_1[0] | reset_IBUF | 4 | 9 |
| clk_IBUF_BUFG | pipe2/E[0] | reset_IBUF | 5 | 9 |
| clk_IBUF_BUFG | | | 3 | 18 |
| clk_IBUF_BUFG | | reset_IBUF | 15 | 34 |
+----------------+------------------------+------------------+------------------+----------------+

2
lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:42:28 2019
| Date : Thu Apr 11 19:41:39 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
| Design : CPU9bits

2
lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:43:03 2019
| Date : Thu Apr 11 19:42:14 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
| Design : CPU9bits

2
lab2CA.runs/impl_1/CPU9bits_io_placed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:42:32 2019
| Date : Thu Apr 11 19:41:43 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_io -file CPU9bits_io_placed.rpt
| Design : CPU9bits

BIN
lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.pb
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Binary file not shown.

614
lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:43:04 2019
| Date : Thu Apr 11 19:42:15 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
| Design : CPU9bits
@@ -23,833 +23,363 @@ Table of Contents
Floorplan: design_1
Design limits: <entire design considered>
Max violations: <unlimited>
Violations found: 164
Violations found: 70
+-----------+----------+-----------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+----------+-----------------------------+------------+
| TIMING-17 | Warning | Non-clocked sequential cell | 164 |
| TIMING-17 | Warning | Non-clocked sequential cell | 70 |
+-----------+----------+-----------------------------+------------+
2. REPORT DETAILS
-----------------
TIMING-17#1 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r0/Dout_reg[0]/C is not reached by a timing clock
The clock pin EM/dM/memory_reg_0_1_0_0/SP/CLK is not reached by a timing clock
Related violations: <none>
TIMING-17#2 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r0/Dout_reg[1]/C is not reached by a timing clock
The clock pin EM/dM/memory_reg_0_1_1_1/SP/CLK is not reached by a timing clock
Related violations: <none>
TIMING-17#3 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r0/Dout_reg[2]/C is not reached by a timing clock
The clock pin EM/dM/memory_reg_0_1_2_2/SP/CLK is not reached by a timing clock
Related violations: <none>
TIMING-17#4 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r0/Dout_reg[3]/C is not reached by a timing clock
The clock pin EM/dM/memory_reg_0_1_3_3/SP/CLK is not reached by a timing clock
Related violations: <none>
TIMING-17#5 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r0/Dout_reg[4]/C is not reached by a timing clock
The clock pin EM/dM/memory_reg_0_1_4_4/SP/CLK is not reached by a timing clock
Related violations: <none>
TIMING-17#6 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r0/Dout_reg[5]/C is not reached by a timing clock
The clock pin EM/dM/memory_reg_0_1_5_5/SP/CLK is not reached by a timing clock
Related violations: <none>
TIMING-17#7 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r0/Dout_reg[6]/C is not reached by a timing clock
The clock pin EM/dM/memory_reg_0_1_6_6/SP/CLK is not reached by a timing clock
Related violations: <none>
TIMING-17#8 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r0/Dout_reg[7]/C is not reached by a timing clock
The clock pin EM/dM/memory_reg_0_1_7_7/SP/CLK is not reached by a timing clock
Related violations: <none>
TIMING-17#9 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r0/Dout_reg[8]/C is not reached by a timing clock
The clock pin EM/dM/memory_reg_0_1_8_8/SP/CLK is not reached by a timing clock
Related violations: <none>
TIMING-17#10 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r1/Dout_reg[0]/C is not reached by a timing clock
The clock pin EM/dM/readData_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#11 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r1/Dout_reg[1]/C is not reached by a timing clock
The clock pin EM/dM/readData_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#12 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r1/Dout_reg[2]/C is not reached by a timing clock
The clock pin EM/dM/readData_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#13 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r1/Dout_reg[3]/C is not reached by a timing clock
The clock pin EM/dM/readData_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#14 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r1/Dout_reg[4]/C is not reached by a timing clock
The clock pin EM/dM/readData_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#15 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r1/Dout_reg[5]/C is not reached by a timing clock
The clock pin EM/dM/readData_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#16 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r1/Dout_reg[6]/C is not reached by a timing clock
The clock pin EM/dM/readData_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#17 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r1/Dout_reg[7]/C is not reached by a timing clock
The clock pin EM/dM/readData_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#18 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r1/Dout_reg[8]/C is not reached by a timing clock
The clock pin EM/dM/readData_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#19 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r2/Dout_reg[0]/C is not reached by a timing clock
The clock pin FD/FetchU/PC/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#20 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r2/Dout_reg[1]/C is not reached by a timing clock
The clock pin FD/FetchU/PC/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#21 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r2/Dout_reg[2]/C is not reached by a timing clock
The clock pin FD/FetchU/PC/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#22 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r2/Dout_reg[3]/C is not reached by a timing clock
The clock pin FD/RF/r0/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#23 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r2/Dout_reg[4]/C is not reached by a timing clock
The clock pin FD/RF/r0/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#24 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r2/Dout_reg[5]/C is not reached by a timing clock
The clock pin FD/RF/r0/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#25 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r2/Dout_reg[6]/C is not reached by a timing clock
The clock pin FD/RF/r0/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#26 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r2/Dout_reg[7]/C is not reached by a timing clock
The clock pin FD/RF/r0/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#27 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r2/Dout_reg[8]/C is not reached by a timing clock
The clock pin FD/RF/r0/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#28 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r3/Dout_reg[0]/C is not reached by a timing clock
The clock pin FD/RF/r0/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#29 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r3/Dout_reg[1]/C is not reached by a timing clock
The clock pin FD/RF/r0/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#30 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r3/Dout_reg[2]/C is not reached by a timing clock
The clock pin FD/RF/r0/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#31 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r3/Dout_reg[3]/C is not reached by a timing clock
The clock pin FD/RF/r1/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#32 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r3/Dout_reg[4]/C is not reached by a timing clock
The clock pin FD/RF/r1/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#33 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r3/Dout_reg[5]/C is not reached by a timing clock
The clock pin FD/RF/r1/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#34 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r3/Dout_reg[6]/C is not reached by a timing clock
The clock pin FD/RF/r1/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#35 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r3/Dout_reg[7]/C is not reached by a timing clock
The clock pin FD/RF/r1/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#36 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r3/Dout_reg[8]/C is not reached by a timing clock
The clock pin FD/RF/r1/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#37 Warning
Non-clocked sequential cell
The clock pin EM/dM/memory_reg/CLKARDCLK is not reached by a timing clock
The clock pin FD/RF/r1/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#38 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[0]/C is not reached by a timing clock
The clock pin FD/RF/r1/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#39 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[1]/C is not reached by a timing clock
The clock pin FD/RF/r1/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#40 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[2]/C is not reached by a timing clock
The clock pin pipe1/Dout_reg[12]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#41 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[3]/C is not reached by a timing clock
The clock pin pipe1/Dout_reg[13]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#42 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[4]/C is not reached by a timing clock
The clock pin pipe1/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#43 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[5]/C is not reached by a timing clock
The clock pin pipe1/Dout_reg[45]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#44 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[6]/C is not reached by a timing clock
The clock pin pipe1/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#45 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[7]/C is not reached by a timing clock
The clock pin pipe1/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#46 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[8]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#47 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[0]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[16]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#48 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[1]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[17]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#49 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[2]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[18]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#50 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[3]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[19]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#51 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[4]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[20]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#52 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[5]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[21]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#53 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[6]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[22]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#54 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[7]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[23]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#55 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[8]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[24]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#56 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[0]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[25]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#57 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[1]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[26]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#58 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[2]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[27]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#59 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[3]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[28]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#60 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[4]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[29]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#61 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[5]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[30]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#62 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[6]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[31]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#63 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[7]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[32]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#64 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[8]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[33]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#65 Warning
Non-clocked sequential cell
The clock pin FD/RF/r2/Dout_reg[0]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[34]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#66 Warning
Non-clocked sequential cell
The clock pin FD/RF/r2/Dout_reg[1]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[35]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#67 Warning
Non-clocked sequential cell
The clock pin FD/RF/r2/Dout_reg[2]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[36]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#68 Warning
Non-clocked sequential cell
The clock pin FD/RF/r2/Dout_reg[3]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#69 Warning
Non-clocked sequential cell
The clock pin FD/RF/r2/Dout_reg[4]/C is not reached by a timing clock
The clock pin pipe2/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#70 Warning
Non-clocked sequential cell
The clock pin FD/RF/r2/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#71 Warning
Non-clocked sequential cell
The clock pin FD/RF/r2/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#72 Warning
Non-clocked sequential cell
The clock pin FD/RF/r2/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#73 Warning
Non-clocked sequential cell
The clock pin FD/RF/r2/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#74 Warning
Non-clocked sequential cell
The clock pin FD/RF/r3/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#75 Warning
Non-clocked sequential cell
The clock pin FD/RF/r3/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#76 Warning
Non-clocked sequential cell
The clock pin FD/RF/r3/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#77 Warning
Non-clocked sequential cell
The clock pin FD/RF/r3/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#78 Warning
Non-clocked sequential cell
The clock pin FD/RF/r3/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#79 Warning
Non-clocked sequential cell
The clock pin FD/RF/r3/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#80 Warning
Non-clocked sequential cell
The clock pin FD/RF/r3/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#81 Warning
Non-clocked sequential cell
The clock pin FD/RF/r3/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#82 Warning
Non-clocked sequential cell
The clock pin FD/RF/r3/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#83 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#84 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[10]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#85 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[11]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#86 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[12]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#87 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[13]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#88 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[14]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#89 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[15]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#90 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[16]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#91 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[17]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#92 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[18]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#93 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[19]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#94 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#95 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[20]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#96 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[21]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#97 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[22]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#98 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[23]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#99 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#100 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#101 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[42]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#102 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[43]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#103 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[44]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#104 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[45]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#105 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[46]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#106 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#107 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#108 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#109 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#110 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#111 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[9]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#112 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#113 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[10]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#114 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[11]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#115 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[12]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#116 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[13]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#117 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[14]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#118 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[15]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#119 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#120 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[25]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#121 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[26]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#122 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[27]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#123 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[28]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#124 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[29]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#125 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#126 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[30]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#127 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[31]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#128 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[32]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#129 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[33]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#130 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[34]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#131 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[35]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#132 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[36]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#133 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[37]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#134 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[38]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#135 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[39]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#136 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#137 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[40]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#138 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[41]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#139 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[42]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#140 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[43]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#141 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[44]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#142 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[45]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#143 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[46]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#144 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[47]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#145 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[48]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#146 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[49]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#147 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#148 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[50]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#149 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[51]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#150 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[52]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#151 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[53]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#152 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[54]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#153 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[55]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#154 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[56]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#155 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[57]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#156 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[58]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#157 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[59]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#158 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#159 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[60]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#160 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[61]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#161 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#162 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#163 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#164 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[9]/C is not reached by a timing clock
Related violations: <none>

BIN
lab2CA.runs/impl_1/CPU9bits_opt.dcp
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lab2CA.runs/impl_1/CPU9bits_placed.dcp
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94
lab2CA.runs/impl_1/CPU9bits_power_routed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:43:05 2019
| Date : Thu Apr 11 19:42:15 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
| Design : CPU9bits
@@ -30,14 +30,14 @@ Table of Contents
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 15.838 |
| Total On-Chip Power (W) | 11.381 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 15.645 |
| Device Static (W) | 0.193 |
| Dynamic (W) | 11.237 |
| Device Static (W) | 0.144 |
| Effective TJA (C/W) | 2.5 |
| Max Ambient (C) | 60.8 |
| Junction Temperature (C) | 64.2 |
| Max Ambient (C) | 71.8 |
| Junction Temperature (C) | 53.2 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
@@ -49,21 +49,21 @@ Table of Contents
1.1 On-Chip Components
----------------------
+----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Slice Logic | 3.275 | 396 | --- | --- |
| LUT as Logic | 3.190 | 184 | 101400 | 0.18 |
| Register | 0.073 | 163 | 202800 | 0.08 |
| F7/F8 Muxes | 0.007 | 3 | 101400 | <0.01 |
| BUFG | 0.005 | 1 | 32 | 3.13 |
| Others | 0.000 | 5 | --- | --- |
| Signals | 3.308 | 335 | --- | --- |
| Block RAM | 0.061 | 0.5 | 325 | 0.15 |
| I/O | 9.001 | 12 | 285 | 4.21 |
| Static Power | 0.193 | | | |
| Total | 15.838 | | | |
+----------------+-----------+----------+-----------+-----------------+
+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Slice Logic | 1.762 | 175 | --- | --- |
| LUT as Logic | 1.689 | 83 | 101400 | 0.08 |
| Register | 0.045 | 61 | 202800 | 0.03 |
| LUT as Distributed RAM | 0.020 | 9 | 35000 | 0.03 |
| BUFG | 0.005 | 1 | 32 | 3.13 |
| F7/F8 Muxes | 0.003 | 1 | 101400 | <0.01 |
| Others | 0.000 | 7 | --- | --- |
| Signals | 1.630 | 143 | --- | --- |
| I/O | 7.846 | 12 | 285 | 4.21 |
| Static Power | 0.144 | | | |
| Total | 11.381 | | | |
+--------------------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
@@ -72,16 +72,16 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint | 0.950 | 7.112 | 6.993 | 0.120 |
| Vccaux | 1.800 | 0.760 | 0.737 | 0.024 |
| Vccint | 0.950 | 3.650 | 3.574 | 0.075 |
| Vccaux | 1.800 | 0.662 | 0.642 | 0.020 |
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 4.263 | 4.262 | 0.001 |
| Vcco18 | 1.800 | 3.716 | 3.715 | 0.001 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
| Vccbram | 0.950 | 0.008 | 0.005 | 0.003 |
| Vccbram | 0.950 | 0.002 | 0.000 | 0.002 |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 |
@@ -137,25 +137,29 @@ Table of Contents
3.1 By Hierarchy
----------------
+------------+-----------+
| Name | Power (W) |
+------------+-----------+
| CPU9bits | 15.645 |
| EM | 0.129 |
| Bank | 0.037 |
| r0 | 0.034 |
| r1 | 0.003 |
| dM | 0.091 |
| FD | 4.742 |
| FetchU | 3.925 |
| PC | 3.925 |
| RF | 0.817 |
| r0 | 0.185 |
| r1 | 0.449 |
| r2 | 0.181 |
| r3 | 0.002 |
| pipe1 | 0.848 |
| pipe2 | 0.903 |
+------------+-----------+
+--------------------------+-----------+
| Name | Power (W) |
+--------------------------+-----------+
| CPU9bits | 11.237 |
| EM | 0.071 |
| dM | 0.071 |
| memory_reg_0_1_0_0 | 0.002 |
| memory_reg_0_1_1_1 | 0.002 |
| memory_reg_0_1_2_2 | 0.002 |
| memory_reg_0_1_3_3 | 0.002 |
| memory_reg_0_1_4_4 | 0.002 |
| memory_reg_0_1_5_5 | 0.002 |
| memory_reg_0_1_6_6 | 0.002 |
| memory_reg_0_1_7_7 | 0.002 |
| memory_reg_0_1_8_8 | 0.002 |
| FD | 2.780 |
| FetchU | 2.642 |
| PC | 2.642 |
| RF | 0.138 |
| r0 | 0.059 |
| r1 | 0.079 |
| pipe1 | 0.093 |
| pipe2 | 0.430 |
+--------------------------+-----------+

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lab2CA.runs/impl_1/CPU9bits_power_summary_routed.pb
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lab2CA.runs/impl_1/CPU9bits_route_status.pb
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10
lab2CA.runs/impl_1/CPU9bits_route_status.rpt
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@@ -1,11 +1,11 @@
Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 416 :
# of nets not needing routing.......... : 79 :
# of internally routed nets........ : 79 :
# of routable nets..................... : 337 :
# of fully routed nets............. : 337 :
# of logical nets.......................... : 184 :
# of nets not needing routing.......... : 39 :
# of internally routed nets........ : 39 :
# of routable nets..................... : 145 :
# of fully routed nets............. : 145 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

BIN
lab2CA.runs/impl_1/CPU9bits_routed.dcp
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8
lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:43:05 2019
| Date : Thu Apr 11 19:42:15 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation
| Design : CPU9bits
@@ -52,7 +52,7 @@ Table of Contents
1. checking no_clock
--------------------
There are 164 register/latch pins with no clock driven by root clock pin: clk (HIGH)
There are 70 register/latch pins with no clock driven by root clock pin: clk (HIGH)
2. checking constant_clock
@@ -67,7 +67,7 @@ Table of Contents
4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 417 pins that are not constrained for maximum delay. (HIGH)
There are 148 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
@@ -81,7 +81,7 @@ Table of Contents
6. checking no_output_delay
---------------------------
There are 10 ports with no output delay specified. (HIGH)
There are 9 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint

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lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:42:32 2019
| Date : Thu Apr 11 19:41:43 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
| Design : CPU9bits
@@ -28,18 +28,20 @@ Table of Contents
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs | 184 | 0 | 101400 | 0.18 |
| LUT as Logic | 184 | 0 | 101400 | 0.18 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 163 | 0 | 202800 | 0.08 |
| Register as Flip Flop | 163 | 0 | 202800 | 0.08 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 3 | 0 | 50700 | <0.01 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+-------------------------+------+-------+-----------+-------+
+----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+------+-------+-----------+-------+
| Slice LUTs | 92 | 0 | 101400 | 0.09 |
| LUT as Logic | 83 | 0 | 101400 | 0.08 |
| LUT as Memory | 9 | 0 | 35000 | 0.03 |
| LUT as Distributed RAM | 9 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| Slice Registers | 61 | 0 | 202800 | 0.03 |
| Register as Flip Flop | 61 | 0 | 202800 | 0.03 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 1 | 0 | 50700 | <0.01 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+----------------------------+------+-------+-----------+-------+
1.1 Summary of Registers by Type
@@ -57,7 +59,7 @@ Table of Contents
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 163 | Yes | Reset | - |
| 61 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -67,22 +69,25 @@ Table of Contents
+--------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+--------------------------------------------+------+-------+-----------+-------+
| Slice | 65 | 0 | 25350 | 0.26 |
| SLICEL | 44 | 0 | | |
| SLICEM | 21 | 0 | | |
| LUT as Logic | 184 | 0 | 101400 | 0.18 |
| Slice | 28 | 0 | 25350 | 0.11 |
| SLICEL | 21 | 0 | | |
| SLICEM | 7 | 0 | | |
| LUT as Logic | 83 | 0 | 101400 | 0.08 |
| using O5 output only | 0 | | | |
| using O6 output only | 144 | | | |
| using O5 and O6 | 40 | | | |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | |
| using O6 output only | 70 | | | |
| using O5 and O6 | 13 | | | |
| LUT as Memory | 9 | 0 | 35000 | 0.03 |
| LUT as Distributed RAM | 9 | 0 | | |
| using O5 output only | 0 | | | |
| using O6 output only | 9 | | | |
| using O5 and O6 | 0 | | | |
| LUT as Shift Register | 0 | 0 | | |
| Slice Registers | 163 | 0 | 202800 | 0.08 |
| Register driven from within the Slice | 68 | | | |
| Register driven from outside the Slice | 95 | | | |
| LUT in front of the register is unused | 46 | | | |
| LUT in front of the register is used | 49 | | | |
| Unique Control Sets | 9 | | 25350 | 0.04 |
| Slice Registers | 61 | 0 | 202800 | 0.03 |
| Register driven from within the Slice | 30 | | | |
| Register driven from outside the Slice | 31 | | | |
| LUT in front of the register is unused | 3 | | | |
| LUT in front of the register is used | 28 | | | |
| Unique Control Sets | 4 | | 25350 | 0.02 |
+--------------------------------------------+------+-------+-----------+-------+
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
@@ -90,14 +95,13 @@ Table of Contents
3. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 0.5 | 0 | 325 | 0.15 |
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
| RAMB18 | 1 | 0 | 650 | 0.15 |
| RAMB18E1 only | 1 | | | |
+-------------------+------+-------+-----------+-------+
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 325 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
| RAMB18 | 0 | 0 | 650 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
@@ -180,17 +184,16 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 163 | Flop & Latch |
| LUT6 | 93 | LUT |
| LUT5 | 52 | LUT |
| LUT3 | 36 | LUT |
| LUT4 | 34 | LUT |
| FDRE | 61 | Flop & Latch |
| LUT6 | 47 | LUT |
| LUT3 | 19 | LUT |
| LUT4 | 14 | LUT |
| LUT5 | 11 | LUT |
| OBUF | 10 | IO |
| LUT2 | 8 | LUT |
| MUXF7 | 3 | MuxFx |
| RAMS32 | 9 | Distributed Memory |
| LUT2 | 5 | LUT |
| IBUF | 2 | IO |
| RAMB18E1 | 1 | Block Memory |
| LUT1 | 1 | LUT |
| MUXF7 | 1 | MuxFx |
| BUFG | 1 | Clock |
+----------+------+---------------------+

4
lab2CA.runs/impl_1/vivado.jou
View File

@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Thu Apr 11 18:41:54 2019
# Process ID: 10352
# Start of session at: Thu Apr 11 19:41:06 2019
# Process ID: 12740
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits.vdi

BIN
lab2CA.runs/impl_1/vivado.pb
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lab2CA.runs/synth_1/CPU9bits.dcp
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1
lab2CA.runs/synth_1/CPU9bits.tcl
View File

@@ -17,7 +17,6 @@ proc create_report { reportName command } {
send_msg_id runtcl-5 warning "$msg"
}
}
set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-3864-DESKTOP-8QFGS52/incrSyn
set_msg_config -id {Synth 8-256} -limit 10000
set_msg_config -id {Synth 8-638} -limit 10000
set_msg_config -id {Vivado 12-818} -string {{WARNING: [Vivado 12-818] No files matched 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/Bank_behav1.wcfg'}} -suppress

179
lab2CA.runs/synth_1/CPU9bits.vds
View File

@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Thu Apr 11 18:41:11 2019
# Process ID: 10636
# Start of session at: Thu Apr 11 19:40:31 2019
# Process ID: 1252
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
@@ -15,9 +15,9 @@ Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 2264
INFO: Helper process launched with PID 12536
---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 359.680 ; gain = 101.758
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 360.711 ; gain = 100.867
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
INFO: [Synth 8-6157] synthesizing module 'FDModule' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v:3]
@@ -93,26 +93,33 @@ INFO: [Synth 8-6155] done synthesizing module 'sign_extend_2bit' (32#1) [C:/User
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (33#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
WARNING: [Synth 8-3331] design dataMemory has unconnected port address[8]
WARNING: [Synth 8-3331] design dataMemory has unconnected port address[7]
WARNING: [Synth 8-3331] design dataMemory has unconnected port address[6]
WARNING: [Synth 8-3331] design dataMemory has unconnected port address[5]
WARNING: [Synth 8-3331] design dataMemory has unconnected port address[4]
WARNING: [Synth 8-3331] design dataMemory has unconnected port address[3]
WARNING: [Synth 8-3331] design dataMemory has unconnected port address[2]
WARNING: [Synth 8-3331] design dataMemory has unconnected port address[1]
WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[50]
WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[49]
WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[48]
WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[47]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.672 ; gain = 157.750
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.168 ; gain = 156.324
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.672 ; gain = 157.750
Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.168 ; gain = 156.324
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k160tifbg484-2L
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.672 ; gain = 157.750
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.168 ; gain = 156.324
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 415.672 ; gain = 157.750
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.168 ; gain = 156.324
---------------------------------------------------------------------------------
INFO: [Synth 8-223] decloning instance 'EM/SE1' (sign_extend_3bit) to 'EM/SE3'
@@ -133,8 +140,9 @@ Detailed RTL Component Info :
51 Bit Registers := 1
9 Bit Registers := 10
+---RAMs :
909 Bit RAMs := 1
18 Bit RAMs := 1
+---Muxes :
7 Input 9 Bit Muxes := 1
2 Input 9 Bit Muxes := 10
4 Input 9 Bit Muxes := 4
2 Input 4 Bit Muxes := 2
@@ -152,6 +160,10 @@ Finished RTL Component Statistics
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module instructionMemory
Detailed RTL Component Info :
+---Muxes :
7 Input 9 Bit Muxes := 1
Module register
Detailed RTL Component Info :
+---Registers :
@@ -190,7 +202,7 @@ Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
+---RAMs :
909 Bit RAMs := 1
18 Bit RAMs := 1
Module bit1_mux_2_1
Detailed RTL Component Info :
+---Muxes :
@@ -216,30 +228,37 @@ No constraint files found.
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[46]' (FDRE) to 'pipe1/Dout_reg[44]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[50]' (FDRE) to 'pipe1/Dout_reg[17]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[48]' (FDRE) to 'pipe1/Dout_reg[17]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[42]' (FDRE) to 'pipe1/Dout_reg[44]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[44]' (FDRE) to 'pipe1/Dout_reg[0]'
INFO: [Synth 8-3886] merging instance 'pipe2/Dout_reg[6]' (FDRE) to 'pipe2/Dout_reg[4]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\pipe1/Dout_reg[0] )
INFO: [Synth 8-3886] merging instance 'pipe2/Dout_reg[4]' (FDRE) to 'pipe1/Dout_reg[0]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\pipe1/Dout_reg[0] )
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[4]' (FDRE) to 'pipe1/Dout_reg[14]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[9]' (FDRE) to 'pipe1/Dout_reg[14]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[14]' (FDRE) to 'pipe1/Dout_reg[11]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\pipe1/Dout_reg[11] )
INFO: [Synth 8-3886] merging instance 'pipe2/Dout_reg[1]' (FDRE) to 'pipe2/Dout_reg[2]'
INFO: [Synth 8-3886] merging instance 'pipe2/Dout_reg[2]' (FDRE) to 'pipe1/Dout_reg[11]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\pipe1/Dout_reg[11] )
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 644.680 ; gain = 386.758
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 622.676 ; gain = 362.832
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
ROM:
+------------------+------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------------+------------+---------------+----------------+
|instructionMemory | p_0_out | 64x9 | LUT |
|CPU9bits | p_0_out | 64x9 | LUT |
+------------------+------------+---------------+----------------+
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+------------------+-----------+----------------------+----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+------------------+-----------+----------------------+----------------+
|CPU9bits | EM/dM/memory_reg | Implied | 2 x 9 | RAM16X1S x 9 |
+------------+------------------+-----------+----------------------+----------------+
Block RAM: Preliminary Mapping Report (see note below)
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|dataMemory: | memory_reg | 128 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
@@ -254,18 +273,18 @@ No constraint files found.
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 644.680 ; gain = 386.758
Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 622.676 ; gain = 362.832
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Block RAM: Final Mapping Report
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|dataMemory: | memory_reg | 128 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
Distributed RAM: Final Mapping Report
+------------+------------------+-----------+----------------------+----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+------------------+-----------+----------------------+----------------+
|CPU9bits | EM/dM/memory_reg | Implied | 2 x 9 | RAM16X1S x 9 |
+------------+------------------+-----------+----------------------+----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
@@ -279,8 +298,13 @@ Report RTL Partitions:
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[10]' (FDRE) to 'pipe1/Dout_reg[3]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[17]' (FDRE) to 'pipe1/Dout_reg[5]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[3]' (FDRE) to 'pipe1/Dout_reg[6]'
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[8]' (FDRE) to 'pipe1/Dout_reg[6]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\pipe1/Dout_reg[6] )
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 644.680 ; gain = 386.758
Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 622.676 ; gain = 362.832
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -304,7 +328,7 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 622.676 ; gain = 362.832
---------------------------------------------------------------------------------
Report Check Netlist:
@@ -317,7 +341,7 @@ Report Check Netlist:
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 622.676 ; gain = 362.832
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -329,25 +353,25 @@ Report RTL Partitions:
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 622.676 ; gain = 362.832
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 622.676 ; gain = 362.832
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 622.676 ; gain = 362.832
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 622.676 ; gain = 362.832
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -364,64 +388,57 @@ Report Cell Usage:
| |Cell |Count |
+------+---------+------+
|1 |BUFG | 1|
|2 |LUT1 | 14|
|3 |LUT2 | 8|
|4 |LUT3 | 36|
|5 |LUT4 | 34|
|6 |LUT5 | 52|
|7 |LUT6 | 93|
|8 |MUXF7 | 3|
|9 |RAMB18E1 | 1|
|10 |FDRE | 163|
|11 |IBUF | 2|
|12 |OBUF | 10|
|2 |LUT2 | 5|
|3 |LUT3 | 18|
|4 |LUT4 | 14|
|5 |LUT5 | 11|
|6 |LUT6 | 47|
|7 |MUXF7 | 2|
|8 |RAM16X1S | 9|
|9 |FDRE | 61|
|10 |IBUF | 2|
|11 |OBUF | 10|
+------+---------+------+
Report Instance Areas:
+------+-----------+-----------+------+
| |Instance |Module |Cells |
+------+-----------+-----------+------+
|1 |top | | 417|
|2 | EM |EMModule | 46|
|3 | Bank |RegFile_4 | 45|
|4 | r0 |register_5 | 17|
|5 | r1 |register_6 | 10|
|6 | r2 |register_7 | 9|
|7 | r3 |register_8 | 9|
|8 | dM |dataMemory | 1|
|9 | FD |FDModule | 207|
|10 | FetchU |FetchUnit | 131|
|11 | PC |register_3 | 131|
|12 | RF |RegFile | 76|
|13 | r0 |register | 18|
|14 | r1 |register_0 | 31|
|15 | r2 |register_1 | 18|
|16 | r3 |register_2 | 9|
|17 | pipe1 |fDPipReg | 73|
|18 | pipe2 |eMPipReg | 78|
|1 |top | | 180|
|2 | EM |EMModule | 18|
|3 | dM |dataMemory | 18|
|4 | FD |FDModule | 106|
|5 | FetchU |FetchUnit | 82|
|6 | PC |register_1 | 82|
|7 | RF |RegFile | 24|
|8 | r0 |register | 11|
|9 | r1 |register_0 | 13|
|10 | pipe1 |fDPipReg | 7|
|11 | pipe2 |eMPipReg | 36|
+------+-----------+-----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 622.676 ; gain = 362.832
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 6 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
Synthesis finished with 0 errors, 0 critical warnings and 12 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 622.676 ; gain = 362.832
Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 622.676 ; gain = 362.832
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.133 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 682.727 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
A total of 9 instances were transformed.
RAM16X1S => RAM32X1S (RAMS32): 9 instances
INFO: [Common 17-83] Releasing license: Synthesis
82 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
104 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:26 . Memory (MB): peak = 681.133 ; gain = 425.672
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.133 ; gain = 0.000
synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 682.727 ; gain = 422.883
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 682.727 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Thu Apr 11 18:41:41 2019...
INFO: [Common 17-206] Exiting Vivado at Thu Apr 11 19:40:59 2019...

BIN
lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
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62
lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:41:41 2019
| Date : Thu Apr 11 19:40:59 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
| Design : CPU9bits
@@ -27,18 +27,20 @@ Table of Contents
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 198 | 0 | 101400 | 0.20 |
| LUT as Logic | 198 | 0 | 101400 | 0.20 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 163 | 0 | 202800 | 0.08 |
| Register as Flip Flop | 163 | 0 | 202800 | 0.08 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 3 | 0 | 50700 | <0.01 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+-------------------------+------+-------+-----------+-------+
+----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+------+-------+-----------+-------+
| Slice LUTs* | 91 | 0 | 101400 | 0.09 |
| LUT as Logic | 82 | 0 | 101400 | 0.08 |
| LUT as Memory | 9 | 0 | 35000 | 0.03 |
| LUT as Distributed RAM | 9 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| Slice Registers | 61 | 0 | 202800 | 0.03 |
| Register as Flip Flop | 61 | 0 | 202800 | 0.03 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 2 | 0 | 50700 | <0.01 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+----------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
@@ -57,21 +59,20 @@ Table of Contents
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 163 | Yes | Reset | - |
| 61 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 0.5 | 0 | 325 | 0.15 |
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
| RAMB18 | 1 | 0 | 650 | 0.15 |
| RAMB18E1 only | 1 | | | |
+-------------------+------+-------+-----------+-------+
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 325 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
| RAMB18 | 0 | 0 | 650 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
@@ -152,17 +153,16 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 163 | Flop & Latch |
| LUT6 | 93 | LUT |
| LUT5 | 52 | LUT |
| LUT3 | 36 | LUT |
| LUT4 | 34 | LUT |
| LUT1 | 14 | LUT |
| FDRE | 61 | Flop & Latch |
| LUT6 | 47 | LUT |
| LUT3 | 18 | LUT |
| LUT4 | 14 | LUT |
| LUT5 | 11 | LUT |
| OBUF | 10 | IO |
| LUT2 | 8 | LUT |
| MUXF7 | 3 | MuxFx |
| RAMS32 | 9 | Distributed Memory |
| LUT2 | 5 | LUT |
| MUXF7 | 2 | MuxFx |
| IBUF | 2 | IO |
| RAMB18E1 | 1 | Block Memory |
| BUFG | 1 | Clock |
+----------+------+---------------------+

2
lab2CA.runs/synth_1/gen_run.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1555022469">
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1555026028">
<File Type="PA-TCL" Name="CPU9bits.tcl"/>
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
<File Type="RDS-RDS" Name="CPU9bits.vds"/>

4
lab2CA.runs/synth_1/vivado.jou
View File

@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Thu Apr 11 18:41:11 2019
# Process ID: 10636
# Start of session at: Thu Apr 11 19:40:31 2019
# Process ID: 1252
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds

28
lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
View File

@@ -1,6 +1,6 @@
webtalk_init -webtalk_dir C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Thu Apr 11 23:44:27 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key date_generated -value "Fri Apr 12 00:01:48 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
@@ -14,7 +14,7 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "17336daf-0d92-4f07-b4a4-ff1c52043edb" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "183" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "184" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-3230M CPU @ 2.60GHz" -context "user_environment"
@@ -22,21 +22,11 @@ webtalk_add_data -client project -key cpu_speed -value "2594 MHz" -context "user
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "8.000 GB" -context "user_environment"
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key File_Counter -value "12" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Simulation_Image_Code -value "121 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Image_Data -value "26 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Processes -value "418" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Instances -value "204" -context "xsim\\usage"
webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Time -value "1.41_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Memory -value "48168_KB" -context "xsim\\usage"
webtalk_transmit -clientid 3886063125 -regid "" -xml C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "215 ns" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.06_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "5928_KB" -context "xsim\\usage"
webtalk_transmit -clientid 442569063 -regid "" -xml C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

2
lab2CA.srcs/sources_1/new/EMModule.v
View File

@@ -1,7 +1,5 @@
`timescale 1ns / 1ps
module EMModule(
input wire reset, clk,
input wire [50:0] PipIn,

23
lab2CA.srcs/sources_1/new/WMUdule.v
View File

@@ -56,3 +56,26 @@ module WMUdule(
.switch(link)
);
endmodule
//module WMUdule_tb();
// reg [61:0] PipIn;
// wire [8:0] RFIn,FUAddr;
// wire [1:0] instr;
// wire fetchBranch, RegEn;
// WMUdule WMUdule_0(
// .PipIn(PipIn),
// .RFIn(RFIn),
// .FUAddr(FUAddr),
// .instr(instr),
// .fetchBranch(fetchBranch),
// .RegEn(RegEn)
// );
// initial begin
// PipIn = 1;
// #5
// $finish;
// end
//endmodule