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This commit is contained in:
jose.rodriguezlabra
2019-04-12 00:02:54 -04:00
parent ddf47c7eee
commit bf57055518
34 changed files with 569 additions and 994 deletions
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lab2CA.runs/impl_1/CPU9bits.vdi
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@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Thu Apr 11 18:41:54 2019
# Process ID: 10352
# Start of session at: Thu Apr 11 19:41:06 2019
# Process ID: 12740
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits.vdi
@@ -13,18 +13,19 @@ source CPU9bits.tcl -notrace
Command: link_design -top CPU9bits -part xc7k160tifbg484-2L
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
INFO: [Project 1-570] Preparing netlist for logic optimization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 578.137 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 578.020 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
A total of 9 instances were transformed.
RAM16X1S => RAM32X1S (RAMS32): 9 instances
6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:16 . Memory (MB): peak = 583.707 ; gain = 330.434
link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:16 . Memory (MB): peak = 578.020 ; gain = 322.695
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
@@ -35,53 +36,53 @@ INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.787 . Memory (MB): peak = 596.723 ; gain = 13.016
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.703 . Memory (MB): peak = 595.879 ; gain = 17.859
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1b0ead489
Ending Cache Timing Information Task | Checksum: 4fc30cd6
Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1152.047 ; gain = 555.324
Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1165.043 ; gain = 569.164
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1075be1b4
Phase 1 Retarget | Checksum: 43f14207
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.123 . Memory (MB): peak = 1249.324 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 13 cells
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1261.125 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 1 cells and removed 1 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 1075be1b4
Phase 2 Constant propagation | Checksum: 43f14207
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.131 . Memory (MB): peak = 1249.324 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1261.125 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 1075be1b4
Phase 3 Sweep | Checksum: 43f14207
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.151 . Memory (MB): peak = 1249.324 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1261.125 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 1075be1b4
Phase 4 BUFG optimization | Checksum: 43f14207
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.163 . Memory (MB): peak = 1249.324 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1261.125 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 1075be1b4
Phase 5 Shift Register Optimization | Checksum: 9334b39a
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.217 . Memory (MB): peak = 1249.324 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.088 . Memory (MB): peak = 1261.125 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 1075be1b4
Phase 6 Post Processing Netlist | Checksum: 9334b39a
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.221 . Memory (MB): peak = 1249.324 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.090 . Memory (MB): peak = 1261.125 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
@@ -90,7 +91,7 @@ Opt_design Change Summary
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 13 | 0 |
| Retarget | 1 | 1 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
@@ -102,50 +103,32 @@ Opt_design Change Summary
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1249.324 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 1075be1b4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.125 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 9334b39a
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.226 . Memory (MB): peak = 1249.324 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.093 . Memory (MB): peak = 1261.125 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.000 | TNS=0.000 |
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
Running Vector-less Activity Propagation...
Ending Power Optimization Task | Checksum: 9334b39a
Finished Running Vector-less Activity Propagation
Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 1 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 2
Ending PowerOpt Patch Enables Task | Checksum: 1075be1b4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1362.293 ; gain = 0.000
Ending Power Optimization Task | Checksum: 1075be1b4
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.918 . Memory (MB): peak = 1362.293 ; gain = 112.969
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1261.125 ; gain = 0.000
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1075be1b4
Ending Final Cleanup Task | Checksum: 9334b39a
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.125 ; gain = 0.000
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.293 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 1075be1b4
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.125 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 9334b39a
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.125 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
28 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
22 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1362.293 ; gain = 778.586
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.293 ; gain = 0.000
opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1261.125 ; gain = 683.105
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.125 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_opt.dcp' has been generated.
@@ -174,127 +157,127 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3d9e6472
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.125 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1963521c
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1362.293 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1261.125 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.125 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15f430561
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 184c2c7e6
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1265.020 ; gain = 3.895
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1c86a0072
Phase 1.3 Build Placer Netlist Model | Checksum: 188e0661e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1265.020 ; gain = 3.895
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1c86a0072
Phase 1.4 Constrain Clocks/Macros | Checksum: 188e0661e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 1c86a0072
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1265.020 ; gain = 3.895
Phase 1 Placer Initialization | Checksum: 188e0661e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1265.020 ; gain = 3.895
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1c86a0072
Phase 2.1 Floorplanning | Checksum: 188e0661e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1266.902 ; gain = 5.777
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
Phase 2 Global Placement | Checksum: 2ac705958
Phase 2 Global Placement | Checksum: 2030f88ae
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1275.738 ; gain = 14.613
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 2ac705958
Phase 3.1 Commit Multi Column Macros | Checksum: 2030f88ae
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1275.738 ; gain = 14.613
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1dbfff5a9
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2ac85731a
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1275.738 ; gain = 14.613
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 21cc4f0ec
Phase 3.3 Area Swap Optimization | Checksum: 1d9aac728
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1275.738 ; gain = 14.613
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 21cc4f0ec
Phase 3.4 Pipeline Register Optimization | Checksum: 1d9aac728
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1275.738 ; gain = 14.613
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 206a7ccd0
Phase 3.5 Small Shape Detail Placement | Checksum: 2ad3da515
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 206a7ccd0
Phase 3.6 Re-assign LUT pins | Checksum: 2ad3da515
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 206a7ccd0
Phase 3.7 Pipeline Register Optimization | Checksum: 2ad3da515
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 3 Detail Placement | Checksum: 206a7ccd0
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
Phase 3 Detail Placement | Checksum: 2ad3da515
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: 206a7ccd0
Phase 4.1 Post Commit Optimization | Checksum: 2ad3da515
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 206a7ccd0
Phase 4.2 Post Placement Cleanup | Checksum: 2ad3da515
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 206a7ccd0
Phase 4.3 Placer Reporting | Checksum: 2ad3da515
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 1f13c29b7
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1284.789 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 2a7ff8ccd
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f13c29b7
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2a7ff8ccd
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Ending Placer Task | Checksum: 161b453db
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
Ending Placer Task | Checksum: 1c01f6f47
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1284.789 ; gain = 23.664
INFO: [Common 17-83] Releasing license: Implementation
45 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
39 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.293 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1284.789 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.117 . Memory (MB): peak = 1362.293 ; gain = 0.000
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.111 . Memory (MB): peak = 1284.789 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file CPU9bits_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1362.293 ; gain = 0.000
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1284.789 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1362.293 ; gain = 0.000
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1284.789 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
@@ -306,68 +289,68 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: b86b4c57 ConstDB: 0 ShapeSum: a9490784 RouteDB: 0
Checksum: PlaceDB: e1291a6d ConstDB: 0 ShapeSum: def654da RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 12dabf8e5
Phase 1 Build RT Design | Checksum: f4f19886
Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1499.332 ; gain = 137.039
Post Restoration Checksum: NetGraph: 45c7ac9c NumContArr: e7e44c49 Constraints: 0 Timing: 0
Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1500.094 ; gain = 215.305
Post Restoration Checksum: NetGraph: 4b3a30b8 NumContArr: a9b767ce Constraints: 0 Timing: 0
Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 12dabf8e5
Phase 2.1 Fix Topology Constraints | Checksum: f4f19886
Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1504.012 ; gain = 141.719
Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1504.246 ; gain = 219.457
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 12dabf8e5
Phase 2.2 Pre Route Cleanup | Checksum: f4f19886
Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1504.012 ; gain = 141.719
Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1504.246 ; gain = 219.457
Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: d6870417
Phase 2 Router Initialization | Checksum: 1793c9dea
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 658f3c2e
Phase 3 Initial Routing | Checksum: 72ce7f92
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 52
Number of Nodes with overlaps = 19
Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: fbcb5761
Phase 4.1 Global Iteration 0 | Checksum: 10c1152b4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Phase 4 Rip-up And Reroute | Checksum: fbcb5761
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Phase 4 Rip-up And Reroute | Checksum: 10c1152b4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: fbcb5761
Phase 5 Delay and Skew Optimization | Checksum: 10c1152b4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: fbcb5761
Phase 6.1 Hold Fix Iter | Checksum: 10c1152b4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Phase 6 Post Hold Fix | Checksum: fbcb5761
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Phase 6 Post Hold Fix | Checksum: 10c1152b4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.0201332 %
Global Horizontal Routing Utilization = 0.0294118 %
Global Vertical Routing Utilization = 0.00697219 %
Global Horizontal Routing Utilization = 0.00971867 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
@@ -377,10 +360,10 @@ Router Utilization Summary
Number of Node Overlaps = 0
Congestion Report
North Dir 1x1 Area, Max Cong = 19.8198%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 18.018%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 29.4118%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 22.0588%, No Congested Regions.
North Dir 1x1 Area, Max Cong = 14.4144%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 14.4144%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 20.5882%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 16.1765%, No Congested Regions.
------------------------------
Reporting congestion hotspots
@@ -402,38 +385,38 @@ Direction: West
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: fbcb5761
Phase 7 Route finalize | Checksum: 10c1152b4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: fbcb5761
Phase 8 Verifying routed nets | Checksum: 10c1152b4
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: b44fe7b0
Phase 9 Depositing Routes | Checksum: 10798d720
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1530.906 ; gain = 246.117
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
57 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
51 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 1531.199 ; gain = 168.906
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1531.199 ; gain = 0.000
route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:30 . Memory (MB): peak = 1530.906 ; gain = 246.117
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1530.906 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.090 . Memory (MB): peak = 1531.199 ; gain = 0.000
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1530.906 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
Command: report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
@@ -455,7 +438,7 @@ INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
68 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
62 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation
@@ -468,4 +451,4 @@ INFO: [runtcl-4] Executing : report_clock_utilization -file CPU9bits_clock_utili
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Thu Apr 11 18:43:05 2019...
INFO: [Common 17-206] Exiting Vivado at Thu Apr 11 19:42:15 2019...