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jose.rodriguezlabra
2019-04-12 00:02:54 -04:00
parent ddf47c7eee
commit bf57055518
34 changed files with 569 additions and 994 deletions
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62
lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:41:41 2019
| Date : Thu Apr 11 19:40:59 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
| Design : CPU9bits
@@ -27,18 +27,20 @@ Table of Contents
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 198 | 0 | 101400 | 0.20 |
| LUT as Logic | 198 | 0 | 101400 | 0.20 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 163 | 0 | 202800 | 0.08 |
| Register as Flip Flop | 163 | 0 | 202800 | 0.08 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 3 | 0 | 50700 | <0.01 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+-------------------------+------+-------+-----------+-------+
+----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+------+-------+-----------+-------+
| Slice LUTs* | 91 | 0 | 101400 | 0.09 |
| LUT as Logic | 82 | 0 | 101400 | 0.08 |
| LUT as Memory | 9 | 0 | 35000 | 0.03 |
| LUT as Distributed RAM | 9 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| Slice Registers | 61 | 0 | 202800 | 0.03 |
| Register as Flip Flop | 61 | 0 | 202800 | 0.03 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 2 | 0 | 50700 | <0.01 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+----------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
@@ -57,21 +59,20 @@ Table of Contents
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 163 | Yes | Reset | - |
| 61 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 0.5 | 0 | 325 | 0.15 |
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
| RAMB18 | 1 | 0 | 650 | 0.15 |
| RAMB18E1 only | 1 | | | |
+-------------------+------+-------+-----------+-------+
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 325 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
| RAMB18 | 0 | 0 | 650 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
@@ -152,17 +153,16 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 163 | Flop & Latch |
| LUT6 | 93 | LUT |
| LUT5 | 52 | LUT |
| LUT3 | 36 | LUT |
| LUT4 | 34 | LUT |
| LUT1 | 14 | LUT |
| FDRE | 61 | Flop & Latch |
| LUT6 | 47 | LUT |
| LUT3 | 18 | LUT |
| LUT4 | 14 | LUT |
| LUT5 | 11 | LUT |
| OBUF | 10 | IO |
| LUT2 | 8 | LUT |
| MUXF7 | 3 | MuxFx |
| RAMS32 | 9 | Distributed Memory |
| LUT2 | 5 | LUT |
| MUXF7 | 2 | MuxFx |
| IBUF | 2 | IO |
| RAMB18E1 | 1 | Block Memory |
| BUFG | 1 | Clock |
+----------+------+---------------------+