William/WMU-ECE-3570-Lab
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Tested the instructions using the instruction memory

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All of the instructions seem to be working other than beq. I might just be calling it wrong
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Johannes
2019-03-20 12:08:24 -04:00
parent 0f55e62a2e
commit c85ad153dc
57 changed files with 3322 additions and 128 deletions
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lab2CA.sim/sim_1/behav/xsim/CPU9bits_tb_vlog.prj
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@@ -5,6 +5,8 @@ verilog xil_defaultlib \
"../../../../lab2CA.srcs/sources_1/new/ControlUnit.v" \
"../../../../lab2CA.srcs/sources_1/new/FetchUnit.v" \
"../../../../lab2CA.srcs/sources_1/new/RegFile.v" \
"../../../../lab2CA.srcs/sources_1/new/dataMemory.v" \
"../../../../lab2CA.srcs/sources_1/new/instructionMemory.v" \
"../../../../lab2CA.srcs/sources_1/new/CPU9bits.v" \
# compile glbl module