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Added 9-bit NOT

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WilliamMiceli
2019-02-15 15:20:12 -05:00
parent 8b37bee087
commit cadbc4dd25
1 changed files with 50 additions and 8 deletions
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58
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -168,14 +168,6 @@ module gen_clock();
endmodule endmodule
module inverter(
input wire A,
output wire B);
assign B = ~A;
endmodule
module mux_4_1(input wire [1:0] switch, module mux_4_1(input wire [1:0] switch,
input wire [8:0] A,B,C,D, input wire [8:0] A,B,C,D,
output reg [8:0] out); output reg [8:0] out);
@@ -191,6 +183,56 @@ module mux_4_1(input wire [1:0] switch,
endmodule endmodule
module not_1bit(
input wire A,
output wire B);
assign B = ~A;
endmodule
module not_9bit(
input wire [8:0] A,
output wire [8:0] B);
not_1bit not0(
.A(A[0])
.B(B[0]));
not_1bit not1(
.A(A[1])
.B(B[1]));
not_1bit not2(
.A(A[2])
.B(B[2]));
not_1bit not3(
.A(A[3])
.B(B[3]));
not_1bit not4(
.A(A[4])
.B(B[4]));
not_1bit not5(
.A(A[5])
.B(B[5]));
not_1bit not6(
.A(A[6])
.B(B[6]));
not_1bit not7(
.A(A[7])
.B(B[7]));
not_1bit not8(
.A(A[8])
.B(B[8]));
endmodule
module register(input wire clk, reset, module register(input wire clk, reset,
input wire [1:0] En, input wire [1:0] En,
input wire [8:0] Din, input wire [8:0] Din,