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I added a comparator, I updated the control unit so that it now uses the 4 bit ALU opcode instead of the 3 bit from before. I added testbenches to the control unit and the slt and comparator modules. However, like before I unable to run the simulation on my desktop. Finally, i added the program code for the equation solver as a test bench in the CPU9bit module
This commit is contained in:
Johannes
2019-03-12 21:14:27 -04:00
parent 3f01492398
commit cb91f6656a
29 changed files with 448 additions and 115 deletions
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4
lab2CA.srcs/sources_1/new/ALU.v
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@@ -53,6 +53,10 @@ module ALU(
.A(operand0),
.B(result_I));
// J (1001)
slt slt0(
.inA(operand0),
.inB(operand1),
.outA(result));
// K (1010)
// L (1011)
// M (1100)

55
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -215,6 +215,49 @@ module and9bit_tb();
end
endmodule
module comparator (
input wire [8:0] A,
input wire [8:0] B,
output wire [8:0] C);
assign C = (~A & ~B) | (A & B);
endmodule
//testbench
module comparator_tb();
reg [8:0] a,b;
wire [8:0] c;
comparator comparator0(
.A(a),
.B(b),
.C(c));
initial begin
a = 9'b000000000;
b = 9'b000000000;
#5
a = 9'b000000000;
b = 9'b000000001;
#5
a = 9'b000000001;
b = 9'b000000000;
#5
a = 9'b000000001;
b = 9'b000000001;
#5
a = 9'b000100001;
b = 9'b000000001;
#5
a = 9'b000100001;
b = 9'b000100001;
#5
$finish;
end
endmodule
module decoder (
input wire en,
input wire [1:0] index,
@@ -887,36 +930,30 @@ endmodule
module slt (
input wire en,
input wire [8:0] inA, inB,
output reg outA);
output reg [8:0] outA);
always @(inA, inB)begin
if (inA < inB) begin
outA = 1;
outA = 9'b000000001;
end
else begin
outA = 0;
outA = 9'b000000000;
end
end
endmodule
//testbench
module slt_tb();
reg enable;
reg [8:0] indexA;
reg [8:0] indexB;
wire outputA;
slt slt0(
.en(enable),
.inA(indexA),
.inB(indexB),
.outA(outputA));
initial begin
enable = 0;
#5
enable = 1;
#5
indexA = 9'b000000000;
indexB = 9'b000000000;
#10

40
lab2CA.srcs/sources_1/new/CPU9bits.v
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@@ -88,4 +88,44 @@ module CPU9bits(input wire [8:0] instr,
.switch(loadS));
endmodule
module CPU9bits_tb();
reg [8:0] instruction;
reg clk, reset;
wire done;
initial begin
clk = 1'b0;
end
always begin
#5 clk = ~clk; // Period to be determined
end
CPU9bits CPU9bits0(
.instr(instruction),
.reset(reset),
.clk(clk),
.done(done));
initial begin
reset = 0;
#10
reset = 1;
#10
instruction = 000100000;
#10
instruction = 000101001;
#10
instruction = 010100010;
#10
instruction = 111100000;
#10
instruction = 111100000;
#10
instruction = 000000000;
#10
$finish;
end
endmodule

101
lab2CA.srcs/sources_1/new/ControlUnit.v
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@@ -3,72 +3,133 @@
module ControlUnit(
input wire [3:0] instIn,
input wire functBit,
output reg [2:0] aluOut,
output reg [3:0] aluOut,
output reg [2:0] FU,
output reg addi,
output reg mem,
output reg load,
output reg RegEn
);
output reg RegEn);
always @(instIn)begin
case(instIn)
4'b0101:
if(functBit == 1) begin
aluOut <= 3'b001; //sub
aluOut <= 4'b0001; //sub
RegEn <= 1'b0;
end
else begin
aluOut <= 3'b000; //Add
aluOut <= 4'b0000; //Add
RegEn <= 1'b0;
end
4'b0111: begin
aluOut <= 3'b111; //nor
4'b1101: begin
aluOut <= 4'b0011; //nor
RegEn <= 1'b0;
end
4'b1110:
if(functBit == 1) begin
aluOut <= 3'b100; //and
aluOut <= 4'b0100; //and
RegEn <= 1'b0;
end
else begin
aluOut <= 3'b010; //or
aluOut <= 4'b0010; //or
RegEn <= 1'b0;
end
4'b1111:
if(functBit == 1) begin
aluOut <= 3'b110; //srl
aluOut <= 4'b0110; //srl
RegEn <= 1'b0;
end
else begin
aluOut <= 3'b101; //sll
aluOut <= 4'b0101; //shift left
RegEn <= 1'b0;
end
4'b0111: begin
aluOut <= 4'b1001; //slt
RegEn <= 1'b0;
end
4'b0110: begin
addi <= 1'b1; // addi
RegEn <= 1'b0;
end
end
4'b1001: begin
FU <= 3'b010; // jump
RegEn <= 1'b1;
end
end
4'b1100: begin
FU <= 3'b011; // branch
RegEn <= 1'b1;
end
end
4'b1000: begin
FU <= 3'b001; // jumpreg
RegEn <= 1'b1;
end
end
4'b0001: begin
mem <= 1'b0; // load
RegEn <= 1'b0;
end
end
4'b0010: begin
mem <= 1'b1; // store
RegEn <= 1'b1;
end
default: aluOut <= 3'bxxxx;
end
default: aluOut <= 4'bxxxx;
endcase
end
endmodule
end
endmodule
module ControlUnit_tb();
reg [3:0] instruction;
reg functionB;
wire [3:0] aluOutput;
wire [2:0] FetchUnit;
wire addImmediate;
wire memory;
wire loadIt;
wire RegEnable;
ControlUnit ControlUnit0(
.instIn(instruction),
.functBit(functionB),
.aluOut(aluOutput),
.FU(FetchUnit),
.addi(addImmediate),
.mem(memory),
.load(loadIt),
.RegEn(RegEnable)
);
initial begin
functionB = 1'b0;
instruction = 4'b0101;
#5
functionB = 1'b1;
#5
functionB = 1'b0;
instruction = 4'b1110;
#5
functionB = 1'b1;
#5
functionB = 1'b0;
instruction = 4'b1111;
#5
functionB = 1'b1;
#5
instruction = 4'b0111;
#5
instruction = 4'b0110;
#5
instruction = 4'b1001;
#5
instruction = 4'b1100;
#5
instruction = 4'b1000;
#5
instruction = 4'b0001;
#5
instruction = 4'b0010;
#5
$finish;
end
endmodule