Added SLT
There is a testbench but when I try to run it on my computer it brings up some regFile simulation even though SLT is set to top. Not sure if its my pc or the code
This commit is contained in:
Johannes
@@ -1,14 +1,12 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550680547">
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<File Type="BITSTR-BMM" Name="FetchUnit_bd.bmm"/>
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<File Type="ROUTE-PWR" Name="FetchUnit_power_routed.rpt"/>
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<File Type="PA-TCL" Name="FetchUnit.tcl"/>
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<File Type="OPT-DCP" Name="FetchUnit_opt.dcp"/>
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<File Type="ROUTE-PWR-SUM" Name="FetchUnit_power_summary_routed.pb"/>
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<File Type="BITSTR-BMM" Name="FetchUnit_bd.bmm"/>
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<File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/>
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<File Type="OPT-DCP" Name="FetchUnit_opt.dcp"/>
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<File Type="OPT-HWDEF" Name="FetchUnit.hwdef"/>
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<File Type="BG-BGN" Name="FetchUnit.bgn"/>
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<File Type="PWROPT-DCP" Name="FetchUnit_pwropt.dcp"/>
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<File Type="BG-BGN" Name="FetchUnit.bgn"/>
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<File Type="PLACE-DCP" Name="FetchUnit_placed.dcp"/>
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<File Type="PLACE-PRE-SIMILARITY" Name="FetchUnit_incremental_reuse_pre_placed.rpt"/>
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<File Type="POSTPLACE-PWROPT-DCP" Name="FetchUnit_postplace_pwropt.dcp"/>
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@@ -18,11 +16,8 @@
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<File Type="ROUTE-ERROR-DCP" Name="FetchUnit_routed_error.dcp"/>
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<File Type="ROUTE-DCP" Name="FetchUnit_routed.dcp"/>
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<File Type="ROUTE-BLACKBOX-DCP" Name="FetchUnit_routed_bb.dcp"/>
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<File Type="ROUTE-DRC-RPX" Name="FetchUnit_drc_routed.rpx"/>
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<File Type="BITSTR-LTX" Name="FetchUnit.ltx"/>
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<File Type="ROUTE-METHODOLOGY-DRC" Name="FetchUnit_methodology_drc_routed.rpt"/>
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<File Type="BITSTR-MMI" Name="FetchUnit.mmi"/>
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<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="FetchUnit_methodology_drc_routed.pb"/>
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<File Type="BITSTR-SYSDEF" Name="FetchUnit.sysdef"/>
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<File Type="ROUTE-TIMING-PB" Name="FetchUnit_timing_summary_routed.pb"/>
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<File Type="POSTROUTE-PHYSOPT-DCP" Name="FetchUnit_postroute_physopt.dcp"/>
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@@ -31,25 +26,8 @@
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<File Type="BITSTR-RBT" Name="FetchUnit.rbt"/>
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<File Type="BITSTR-NKY" Name="FetchUnit.nky"/>
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<File Type="BG-DRC" Name="FetchUnit.drc"/>
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<File Type="ROUTE-CLK" Name="FetchUnit_clock_utilization_routed.rpt"/>
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<File Type="RDI-RDI" Name="FetchUnit.vdi"/>
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<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
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<File Type="OPT-DRC" Name="FetchUnit_drc_opted.rpt"/>
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<File Type="PLACE-UTIL" Name="FetchUnit_utilization_placed.rpt"/>
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<File Type="PLACE-UTIL-PB" Name="FetchUnit_utilization_placed.pb"/>
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<File Type="PLACE-IO" Name="FetchUnit_io_placed.rpt"/>
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<File Type="PLACE-CTRL" Name="FetchUnit_control_sets_placed.rpt"/>
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<File Type="ROUTE-TIMINGSUMMARY" Name="FetchUnit_timing_summary_routed.rpt"/>
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<File Type="ROUTE-TIMING-RPX" Name="FetchUnit_timing_summary_routed.rpx"/>
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<File Type="ROUTE-STATUS" Name="FetchUnit_route_status.rpt"/>
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<File Type="ROUTE-STATUS-PB" Name="FetchUnit_route_status.pb"/>
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<File Type="ROUTE-PWR-RPX" Name="FetchUnit_power_routed.rpx"/>
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<File Type="ROUTE-DRC" Name="FetchUnit_drc_routed.rpt"/>
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<File Type="ROUTE-DRC-PB" Name="FetchUnit_drc_routed.pb"/>
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<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="FetchUnit_methodology_drc_routed.rpx"/>
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<File Type="ROUTE-BUS-SKEW" Name="FetchUnit_bus_skew_routed.rpt"/>
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<File Type="ROUTE-BUS-SKEW-RPX" Name="FetchUnit_bus_skew_routed.rpx"/>
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<File Type="ROUTE-BUS-SKEW-PB" Name="FetchUnit_bus_skew_routed.pb"/>
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<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/sources_1/new/BasicModules.v">
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@@ -4,8 +4,6 @@
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<File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/>
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<File Type="RDS-RDS" Name="FetchUnit.vds"/>
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<File Type="RDS-DCP" Name="FetchUnit.dcp"/>
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<File Type="RDS-UTIL" Name="FetchUnit_utilization_synth.rpt"/>
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<File Type="RDS-UTIL-PB" Name="FetchUnit_utilization_synth.pb"/>
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<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/sources_1/new/BasicModules.v">
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11
lab2CA.sim/sim_1/behav/xsim/slt_tb.tcl
Normal file
11
lab2CA.sim/sim_1/behav/xsim/slt_tb.tcl
Normal file
@@ -0,0 +1,11 @@
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set curr_wave [current_wave_config]
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if { [string length $curr_wave] == 0 } {
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if { [llength [get_objects]] > 0} {
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add_wave /
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set_property needs_save false [current_wave_config]
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} else {
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send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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}
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}
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run 1000ns
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9
lab2CA.sim/sim_1/behav/xsim/slt_tb_vlog.prj
Normal file
9
lab2CA.sim/sim_1/behav/xsim/slt_tb_vlog.prj
Normal file
@@ -0,0 +1,9 @@
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# compile verilog/system verilog design source files
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verilog xil_defaultlib \
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"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
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# compile glbl module
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verilog xil_defaultlib "glbl.v"
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# Do not sort compile order
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nosort
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@@ -2,11 +2,11 @@
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# Webtalk v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Wed Feb 27 11:47:34 2019
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# Process ID: 6784
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# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
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# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace
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# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
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# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
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# Start of session at: Tue Mar 12 19:46:24 2019
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# Process ID: 6512
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# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim
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# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace
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# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log
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# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
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#-----------------------------------------------------------
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source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace
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source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace
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12
lab2CA.sim/sim_1/behav/xsim/webtalk_4236.backup.jou
Normal file
12
lab2CA.sim/sim_1/behav/xsim/webtalk_4236.backup.jou
Normal file
@@ -0,0 +1,12 @@
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#-----------------------------------------------------------
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# Webtalk v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Tue Mar 12 19:44:30 2019
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# Process ID: 4236
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# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim
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# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace
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# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log
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# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
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#-----------------------------------------------------------
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source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace
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@@ -1,12 +0,0 @@
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#-----------------------------------------------------------
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# Webtalk v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Thu Feb 21 14:24:16 2019
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# Process ID: 6516
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# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim
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# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace
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# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
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# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
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#-----------------------------------------------------------
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source C:/Users/JoseIgnacio/CA -notrace
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@@ -1,12 +0,0 @@
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#-----------------------------------------------------------
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# Webtalk v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Wed Feb 27 11:36:59 2019
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# Process ID: 7276
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# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
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# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace
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# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
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# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
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#-----------------------------------------------------------
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source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace
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Binary file not shown.
@@ -0,0 +1 @@
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-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "slt_tb_behav" "xil_defaultlib.slt_tb" "xil_defaultlib.glbl" -log "elaborate.log"
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@@ -0,0 +1 @@
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Breakpoint File Version 1.0
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109
lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/obj/xsim_1.c
Normal file
109
lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/obj/xsim_1.c
Normal file
@@ -0,0 +1,109 @@
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/**********************************************************************/
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/* ____ ____ */
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/* / /\/ / */
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/* /___/ \ / */
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/* \ \ \/ */
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/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
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/* / / All Right Reserved. */
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/* /---/ /\ */
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/* \ \ / \ */
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/* \___\/\___\ */
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/**********************************************************************/
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#include "iki.h"
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#include <string.h>
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#include <math.h>
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#ifdef __GNUC__
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#include <stdlib.h>
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#else
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#include <malloc.h>
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#define alloca _alloca
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#endif
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/**********************************************************************/
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/* ____ ____ */
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/* / /\/ / */
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/* /___/ \ / */
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/* \ \ \/ */
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/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
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/* / / All Right Reserved. */
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/* /---/ /\ */
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/* \ \ / \ */
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/* \___\/\___\ */
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/**********************************************************************/
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#include "iki.h"
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#include <string.h>
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#include <math.h>
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#ifdef __GNUC__
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#include <stdlib.h>
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#else
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#include <malloc.h>
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#define alloca _alloca
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#endif
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typedef void (*funcp)(char *, char *);
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extern int main(int, char**);
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extern void execute_4(char*, char *);
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extern void execute_9(char*, char *);
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extern void execute_10(char*, char *);
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extern void execute_11(char*, char *);
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extern void execute_12(char*, char *);
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extern void execute_3(char*, char *);
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extern void execute_6(char*, char *);
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extern void execute_7(char*, char *);
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extern void execute_8(char*, char *);
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extern void execute_13(char*, char *);
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extern void execute_14(char*, char *);
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extern void execute_15(char*, char *);
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extern void execute_16(char*, char *);
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extern void execute_17(char*, char *);
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extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
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funcp funcTab[15] = {(funcp)execute_4, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_3, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)vlog_transfunc_eventcallback};
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const int NumRelocateId= 15;
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void relocate(char *dp)
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{
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iki_relocate(dp, "xsim.dir/slt_tb_behav/xsim.reloc", (void **)funcTab, 15);
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/*Populate the transaction function pointer field in the whole net structure */
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}
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void sensitize(char *dp)
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{
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iki_sensitize(dp, "xsim.dir/slt_tb_behav/xsim.reloc");
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}
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void simulate(char *dp)
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{
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iki_schedule_processes_at_time_zero(dp, "xsim.dir/slt_tb_behav/xsim.reloc");
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// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
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iki_execute_processes();
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// Schedule resolution functions for the multiply driven Verilog nets that have strength
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// Schedule transaction functions for the singly driven Verilog nets that have strength
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}
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#include "iki_bridge.h"
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void relocate(char *);
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void sensitize(char *);
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void simulate(char *);
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extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
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extern void implicit_HDL_SCinstatiate();
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extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
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extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
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int main(int argc, char **argv)
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{
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iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
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iki_set_sv_type_file_path_name("xsim.dir/slt_tb_behav/xsim.svtype");
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iki_set_crvs_dump_file_path_name("xsim.dir/slt_tb_behav/xsim.crvsdump");
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void* design_handle = iki_create_design("xsim.dir/slt_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
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iki_set_rc_trial_count(100);
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(void) design_handle;
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return iki_simulate_design();
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}
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@@ -0,0 +1,43 @@
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<?xml version="1.0" encoding="UTF-8" ?>
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<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Tue Mar 12 19:46:24 2019'>
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<section name="__ROOT__" level="0" order="1" description="">
|
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<section name="software_version_and_target_device" level="1" order="1" description="">
|
||||
<keyValuePair key="beta" value="FALSE" description="" />
|
||||
<keyValuePair key="build_version" value="2405991" description="" />
|
||||
<keyValuePair key="date_generated" value="Tue Mar 12 19:46:23 2019" description="" />
|
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<keyValuePair key="os_platform" value="WIN64" description="" />
|
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<keyValuePair key="product_version" value="XSIM v2018.3 (64-bit)" description="" />
|
||||
<keyValuePair key="project_id" value="0a5803efda44405bb28bbf43ba22e808" description="" />
|
||||
<keyValuePair key="project_iteration" value="2" description="" />
|
||||
<keyValuePair key="random_id" value="fe5d421c9f2b5ebc958da28a6d468b09" description="" />
|
||||
<keyValuePair key="registration_id" value="fe5d421c9f2b5ebc958da28a6d468b09" description="" />
|
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<keyValuePair key="route_design" value="FALSE" description="" />
|
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<keyValuePair key="target_device" value="not_applicable" description="" />
|
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<keyValuePair key="target_family" value="not_applicable" description="" />
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<keyValuePair key="target_package" value="not_applicable" description="" />
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<keyValuePair key="target_speed" value="not_applicable" description="" />
|
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<keyValuePair key="tool_flow" value="xsim_vivado" description="" />
|
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</section>
|
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<section name="user_environment" level="1" order="2" description="">
|
||||
<keyValuePair key="cpu_name" value="Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz" description="" />
|
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<keyValuePair key="cpu_speed" value="3492 MHz" description="" />
|
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<keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
|
||||
<keyValuePair key="os_release" value="major release (build 9200)" description="" />
|
||||
<keyValuePair key="system_ram" value="17.000 GB" description="" />
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||||
<keyValuePair key="total_processors" value="1" description="" />
|
||||
</section>
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<section name="vivado_usage" level="1" order="3" description="">
|
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</section>
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<section name="xsim" level="1" order="4" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="command" value="xsim" description="" />
|
||||
</section>
|
||||
<section name="usage" level="2" order="2" description="">
|
||||
<keyValuePair key="iteration" value="0" description="" />
|
||||
<keyValuePair key="runtime" value="30 ns" description="" />
|
||||
<keyValuePair key="simulation_memory" value="5912_KB" description="" />
|
||||
<keyValuePair key="simulation_time" value="0.06_sec" description="" />
|
||||
</section>
|
||||
</section>
|
||||
</section>
|
||||
</webTalkData>
|
||||
@@ -0,0 +1,42 @@
|
||||
webtalk_init -webtalk_dir C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/
|
||||
webtalk_register_client -client project
|
||||
webtalk_add_data -client project -key date_generated -value "Tue Mar 12 19:48:08 2019" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key random_id -value "fe5d421c9f2b5ebc958da28a6d468b09" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key project_iteration -value "5" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
|
||||
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
|
||||
webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz" -context "user_environment"
|
||||
webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment"
|
||||
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
|
||||
webtalk_add_data -client project -key system_ram -value "17.000 GB" -context "user_environment"
|
||||
webtalk_register_client -client xsim
|
||||
webtalk_add_data -client xsim -key File_Counter -value "2" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key Simulation_Image_Code -value "65 KB" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Simulation_Image_Data -value "2 KB" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Total_Processes -value "17" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Total_Instances -value "3" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Compiler_Time -value "0.62_sec" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Compiler_Memory -value "36408_KB" -context "xsim\\usage"
|
||||
webtalk_transmit -clientid 1095157529 -regid "" -xml C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
|
||||
webtalk_terminate
|
||||
BIN
lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/xsim.mem
Normal file
BIN
lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/xsim.mem
Normal file
Binary file not shown.
Binary file not shown.
11
lab2CA.srcs/sources_1/bd/design_1/design_1.bd
Normal file
11
lab2CA.srcs/sources_1/bd/design_1/design_1.bd
Normal file
@@ -0,0 +1,11 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0x0",
|
||||
"name": "design_1",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2018.3"
|
||||
},
|
||||
"design_tree": {}
|
||||
}
|
||||
}
|
||||
@@ -884,6 +884,52 @@ module shift_right_arithmetic_tb();
|
||||
end
|
||||
endmodule
|
||||
|
||||
module slt (
|
||||
input wire en,
|
||||
input wire [8:0] inA, inB,
|
||||
output reg outA);
|
||||
|
||||
always @(inA, inB)begin
|
||||
if (inA < inB) begin
|
||||
outA = 1;
|
||||
end
|
||||
else begin
|
||||
outA = 0;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
//testbench
|
||||
module slt_tb();
|
||||
reg enable;
|
||||
reg [8:0] indexA;
|
||||
reg [8:0] indexB;
|
||||
wire outputA;
|
||||
|
||||
slt slt0(
|
||||
.en(enable),
|
||||
.inA(indexA),
|
||||
.inB(indexB),
|
||||
.outA(outputA));
|
||||
|
||||
initial begin
|
||||
enable = 0;
|
||||
#5
|
||||
enable = 1;
|
||||
#5
|
||||
indexA = 9'b000000000;
|
||||
indexB = 9'b000000000;
|
||||
#10
|
||||
indexA = 9'b000000000;
|
||||
indexB = 9'b111100000;
|
||||
#10
|
||||
indexA = 9'b000001111;
|
||||
indexB = 9'b000000000;
|
||||
#10
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module sub_9bit(
|
||||
input wire [8:0] A,
|
||||
input wire [8:0] B,
|
||||
|
||||
14
lab2CA.xpr
14
lab2CA.xpr
@@ -3,7 +3,7 @@
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="39" Path="C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr">
|
||||
<Project Version="7" Minor="39" Path="C:/Users/Johannes/ece3570-lab2/lab2CA.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="0a5803efda44405bb28bbf43ba22e808"/>
|
||||
@@ -31,7 +31,7 @@
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="71"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="75"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
@@ -101,6 +101,14 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="CPU9bits"/>
|
||||
@@ -121,7 +129,7 @@
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="regFile_tb"/>
|
||||
<Option Name="TopModule" Val="slt_tb"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
|
||||
Reference in New Issue
Block a user