3f01492398a48acddd7bed9bc49b964142d90ee3
There is a testbench but when I try to run it on my computer it brings up some regFile simulation even though SLT is set to top. Not sure if its my pc or the code
ECE 3570 Lab
Fixes To Be Implemented
- Get rid of the double zero for the enable on the registers
- Make decoder for it
- Redo simulations with other registers using internal signals
- Fix simulation waveforms for Registers, as we are currently changing inputs too quickly (multiple times within a clock cycle)
- Only two registers are being written to, first two within simulation is not being written to
- Need to allow for signed numbers
- Remove subtraction from ALU
- Have arithmetic shift left and right
Uncomment all testbenches(We can have multiple testbenches active at once)- Bitwise operations do not need a 1-bit implementation, modify 9-bit and keep it only
- Comparator needed
- Make subtraction more efficient
- Need to verify that FetchUnit is working properly as Martin had some concerns that it probably wasn't functioning properly
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