CPU
LOTS
This commit is contained in:
@@ -3,7 +3,7 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Thu Feb 21 15:07:11 2019">
|
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<application name="pa" timeStamp="Sun Mar 10 14:09:05 2019">
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<section name="Project Information" visible="false">
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<property name="ProjectID" value="88e779ed22f94d2db93b335d17c75f15" type="ProjectID"/>
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<property name="ProjectIteration" value="7" type="ProjectIteration"/>
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@@ -17,17 +17,18 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
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</item>
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<item name="Java Command Handlers">
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<property name="CloseProject" value="1" type="JavaHandler"/>
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<property name="OpenDesign" value="1" type="JavaHandler"/>
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<property name="OpenProject" value="1" type="JavaHandler"/>
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<property name="OpenProject" value="2" type="JavaHandler"/>
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<property name="ReloadDesign" value="1" type="JavaHandler"/>
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<property name="RunImplementation" value="7" type="JavaHandler"/>
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<property name="RunSchematic" value="9" type="JavaHandler"/>
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<property name="RunSynthesis" value="16" type="JavaHandler"/>
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<property name="SetSourceEnabled" value="2" type="JavaHandler"/>
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<property name="SetTopNode" value="23" type="JavaHandler"/>
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<property name="SetTopNode" value="25" type="JavaHandler"/>
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<property name="ShowView" value="9" type="JavaHandler"/>
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<property name="SimulationClose" value="4" type="JavaHandler"/>
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<property name="SimulationRun" value="63" type="JavaHandler"/>
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<property name="SimulationClose" value="5" type="JavaHandler"/>
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<property name="SimulationRun" value="73" type="JavaHandler"/>
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<property name="ToggleSelectAreaMode" value="2" type="JavaHandler"/>
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<property name="ToolsSettings" value="1" type="JavaHandler"/>
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<property name="ViewTaskImplementation" value="1" type="JavaHandler"/>
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@@ -36,67 +37,74 @@ This means code written to parse this file will need to be revisited each subseq
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<property name="ZoomFit" value="6" type="JavaHandler"/>
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<property name="CmdMsgDialog_OK" value="4" type="GuiHandlerData"/>
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<property name="BaseDialog_YES" value="5" type="GuiHandlerData"/>
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<property name="CmdMsgDialog_OK" value="7" type="GuiHandlerData"/>
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<property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="1" type="GuiHandlerData"/>
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<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="142" type="GuiHandlerData"/>
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<property name="FloatingTopDialog_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="12" type="GuiHandlerData"/>
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<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="121" type="GuiHandlerData"/>
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<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="132" type="GuiHandlerData"/>
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<property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
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<property name="GraphicalView_ZOOM_FIT" value="27" type="GuiHandlerData"/>
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<property name="GraphicalView_ZOOM_IN" value="40" type="GuiHandlerData"/>
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<property name="GraphicalView_ZOOM_OUT" value="28" type="GuiHandlerData"/>
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<property name="HCodeEditor_BLANK_OPERATIONS" value="5" type="GuiHandlerData"/>
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<property name="HCodeEditor_CLOSE" value="4" type="GuiHandlerData"/>
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<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="8" type="GuiHandlerData"/>
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<property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="13" type="GuiHandlerData"/>
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<property name="LaunchPanel_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/>
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<property name="MainMenuMgr_EDIT" value="2" type="GuiHandlerData"/>
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<property name="MainMenuMgr_FILE" value="4" type="GuiHandlerData"/>
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<property name="MainMenuMgr_FLOW" value="2" type="GuiHandlerData"/>
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<property name="MainMenuMgr_PROJECT" value="3" type="GuiHandlerData"/>
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<property name="PACommandNames_AUTO_UPDATE_HIER" value="28" type="GuiHandlerData"/>
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<property name="PACommandNames_CLOSE_PROJECT" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_OPEN_RTL_DESIGN" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_RELOAD_RTL_DESIGN" value="1" type="GuiHandlerData"/>
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<property name="StaleMoreAction_OUT_OF_DATE_DETAILS" value="1" type="GuiHandlerData"/>
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<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="3" type="GuiHandlerData"/>
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<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="6" type="GuiHandlerData"/>
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<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
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<property name="TaskBanner_CLOSE" value="20" type="GuiHandlerData"/>
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<item name="Other">
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<property name="GuiMode" value="61" type="GuiMode"/>
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<property name="GuiMode" value="11" type="GuiMode"/>
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</item>
|
||||
</section>
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||||
</application>
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||||
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||||
@@ -44,7 +44,7 @@ module ALU(
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shift_logical_right slr(
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.A(operand0),
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.B(result_G));
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// H (111)
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// H (111) //slt
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// MUX chooses which result to show based on the ALU's opcode
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@@ -5,43 +5,87 @@ module CPU9bits(input wire [8:0] instr,
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output reg done
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||||
);
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||||
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||||
wire [8:0] op1, op2;
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wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut;
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wire [2:0] FU, aluOp;
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||||
wire addiS, RegEn, loadS;
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||||
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||||
RegFile RF(
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.clk(clk),
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||||
.reset(reset),
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||||
.enable(),
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||||
.write_index(),
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||||
.op0_idx(),
|
||||
.op1_idx(),
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||||
.write_data(),
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||||
.enable(RegEn),
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||||
.write_index(instr[4:3]),
|
||||
.op0_idx(instr[4:3]),
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||||
.op1_idx(instr[2:1]),
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||||
.write_data(RFIn),
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||||
.op0(op0),
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||||
.op1(op1)
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||||
);
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||||
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||||
FetchUnit FU(
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||||
FetchUnit FetchU(
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||||
.clk(clk),
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||||
.reset(reset),
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||||
.op_idx(),
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||||
.AddrIn(),
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||||
.AddrOut()
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||||
.op_idx(FU[0]),
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||||
.AddrIn(FUAddr),
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||||
.AddrOut(PCout)
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||||
);
|
||||
|
||||
ALU alu(
|
||||
.opcode(),
|
||||
.opcode(aluOp),
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||||
.operand0(op0),
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||||
.operand1(op1),
|
||||
.result()
|
||||
.result(AluOut)
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||||
);
|
||||
|
||||
//Make control unit here
|
||||
ControlUnit CU(
|
||||
.instIn(instr[8:5]),
|
||||
.functBit(instr[0]),
|
||||
.aluOut(aluOp),
|
||||
.FU(FU),
|
||||
.addi(addiS),
|
||||
.mem(loadS),
|
||||
.load(loadMux)
|
||||
);
|
||||
|
||||
always @(instr) begin
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||||
case (instr)
|
||||
9'b000000000: //something
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||||
endcase
|
||||
end
|
||||
|
||||
//------------------------------
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||||
//-----------------------Fetch Unit Stuff
|
||||
|
||||
add_9bit JBAdder(
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||||
.A(PCout),
|
||||
.B(JBRes),
|
||||
.Cin(9'b000000000),
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||||
.Sum(FUJB));
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||||
|
||||
mux_2_1 mux1(
|
||||
.A(op1),
|
||||
.B(FUJB),
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||||
.out(FUAddr),
|
||||
.switch(FU[1]));
|
||||
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||||
mux_2_1 mux2(
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||||
.A({4'b0000,instr[4:0]}),
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||||
.B({6'b000000,instr[2:0]}),
|
||||
.out(JBRes),
|
||||
.switch(FU[2]));
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||||
|
||||
///--------------------------Addi Stuff
|
||||
|
||||
add_9bit Addier(
|
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.A({6'b000000,instr[2:0]}),
|
||||
.B(op1),
|
||||
.Cin(9'b000000000),
|
||||
.Sum(AddiOut));
|
||||
|
||||
mux_2_1 mux3(
|
||||
.A(AluOut),
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||||
.B(AddiOut),
|
||||
.out(loadMux),
|
||||
.switch(addiS));
|
||||
|
||||
mux_2_1 mux4(
|
||||
.A(loadMux),
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||||
.B(dataMemOut),
|
||||
.out(RFIn),
|
||||
.switch(loadS));
|
||||
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
74
lab2CA.srcs/sources_1/new/ControlUnit.v
Normal file
74
lab2CA.srcs/sources_1/new/ControlUnit.v
Normal file
@@ -0,0 +1,74 @@
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||||
`timescale 1ns / 1ps
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||||
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||||
module ControlUnit(
|
||||
input wire [3:0] instIn,
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input wire functBit,
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||||
output reg [2:0] aluOut,
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||||
output reg [2:0] FU,
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||||
output reg addi,
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||||
output reg mem,
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||||
output reg load,
|
||||
output reg RegEn
|
||||
);
|
||||
|
||||
always @(instIn)begin
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||||
case(instIn)
|
||||
4'b0101:
|
||||
if(functBit == 1) begin
|
||||
aluOut <= 3'b001; //sub
|
||||
RegEn <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
aluOut <= 3'b000; //Add
|
||||
RegEn <= 1'b0;
|
||||
end
|
||||
4'b0111: begin
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||||
aluOut <= 3'b111; //nor
|
||||
RegEn <= 1'b0;
|
||||
end
|
||||
4'b1110:
|
||||
if(functBit == 1) begin
|
||||
aluOut <= 3'b100; //and
|
||||
RegEn <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
aluOut <= 3'b010; //or
|
||||
RegEn <= 1'b0;
|
||||
end
|
||||
4'b1111:
|
||||
if(functBit == 1) begin
|
||||
aluOut <= 3'b110; //srl
|
||||
RegEn <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
aluOut <= 3'b101; //sll
|
||||
RegEn <= 1'b0;
|
||||
end
|
||||
4'b0110: begin
|
||||
addi <= 1'b1; // addi
|
||||
RegEn <= 1'b0;
|
||||
end
|
||||
4'b1001: begin
|
||||
FU <= 3'b010; // jump
|
||||
RegEn <= 1'b1;
|
||||
end
|
||||
4'b1100: begin
|
||||
FU <= 3'b011; // branch
|
||||
RegEn <= 1'b1;
|
||||
end
|
||||
4'b1000: begin
|
||||
FU <= 3'b001; // jumpreg
|
||||
RegEn <= 1'b1;
|
||||
end
|
||||
4'b0001: begin
|
||||
mem <= 1'b0; // load
|
||||
RegEn <= 1'b0;
|
||||
end
|
||||
4'b0010: begin
|
||||
mem <= 1'b1; // store
|
||||
RegEn <= 1'b1;
|
||||
end
|
||||
default: aluOut <= 3'bxxxx;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
@@ -1,7 +1,7 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module FetchUnit(input wire clk, reset,
|
||||
input wire [1:0] op_idx,
|
||||
input wire op_idx,
|
||||
input wire [8:0] AddrIn,
|
||||
output wire [8:0] AddrOut);
|
||||
|
||||
|
||||
28
lab2CA.xpr
28
lab2CA.xpr
@@ -3,7 +3,7 @@
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="39" Path="C:/Users/JoseIgnacio/CA Lab/lab2CA.xpr">
|
||||
<Project Version="7" Minor="39" Path="C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="0a5803efda44405bb28bbf43ba22e808"/>
|
||||
@@ -59,6 +59,13 @@
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@@ -66,6 +73,13 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/ControlUnit.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/FetchUnit.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@@ -73,17 +87,8 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -91,7 +96,6 @@
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/CPU9bits.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -99,7 +103,7 @@
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="FetchUnit"/>
|
||||
<Option Name="TopModule" Val="CPU9bits"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
|
||||
Reference in New Issue
Block a user