case for control unit

2019-03-10 14:05:21 -04:00
parent 172238b4e0
commit 7406cddb64
1 changed files with 7 additions and 3 deletions
--- a/lab2CA.srcs/sources_1/new/CPU9bits.v
+++ b/lab2CA.srcs/sources_1/new/CPU9bits.v
@@ -1,8 +1,8 @@
 `timescale 1ns / 1ps

 module CPU9bits(input wire [8:0] instr,
-            input wire reset, clk,
-            output reg done
+        input wire reset, clk,
+        output reg done
    );
    
    wire [8:0] op1, op2;
@@ -36,7 +36,11 @@ module CPU9bits(input wire [8:0] instr,
     
     //Make control unit here
     
-     
+     always @(instr) begin
+        case (instr)
+            9'b000000000: //something
+        endcase
+     end
     
     //------------------------------