Many Changes

I added a comparator, I updated the control unit so that it now uses the 4 bit ALU opcode instead of the 3 bit from before. I added testbenches to the control unit and the slt and comparator modules. However, like before I unable to run the simulation on my desktop. Finally, i added the program code for the equation solver as a test bench in the CPU9bit module
This commit is contained in:
Johannes
2019-03-12 21:14:27 -04:00
parent 3f01492398
commit cb91f6656a
29 changed files with 448 additions and 115 deletions

View File

@@ -215,6 +215,49 @@ module and9bit_tb();
end
endmodule
module comparator (
input wire [8:0] A,
input wire [8:0] B,
output wire [8:0] C);
assign C = (~A & ~B) | (A & B);
endmodule
//testbench
module comparator_tb();
reg [8:0] a,b;
wire [8:0] c;
comparator comparator0(
.A(a),
.B(b),
.C(c));
initial begin
a = 9'b000000000;
b = 9'b000000000;
#5
a = 9'b000000000;
b = 9'b000000001;
#5
a = 9'b000000001;
b = 9'b000000000;
#5
a = 9'b000000001;
b = 9'b000000001;
#5
a = 9'b000100001;
b = 9'b000000001;
#5
a = 9'b000100001;
b = 9'b000100001;
#5
$finish;
end
endmodule
module decoder (
input wire en,
input wire [1:0] index,
@@ -887,36 +930,30 @@ endmodule
module slt (
input wire en,
input wire [8:0] inA, inB,
output reg outA);
output reg [8:0] outA);
always @(inA, inB)begin
if (inA < inB) begin
outA = 1;
outA = 9'b000000001;
end
else begin
outA = 0;
outA = 9'b000000000;
end
end
endmodule
//testbench
module slt_tb();
reg enable;
reg [8:0] indexA;
reg [8:0] indexB;
wire outputA;
slt slt0(
.en(enable),
.inA(indexA),
.inB(indexB),
.outA(outputA));
initial begin
enable = 0;
#5
enable = 1;
#5
indexA = 9'b000000000;
indexB = 9'b000000000;
#10