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I added a comparator, I updated the control unit so that it now uses the 4 bit ALU opcode instead of the 3 bit from before. I added testbenches to the control unit and the slt and comparator modules. However, like before I unable to run the simulation on my desktop. Finally, i added the program code for the equation solver as a test bench in the CPU9bit module
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Johannes
2019-03-12 21:14:27 -04:00
parent 3f01492398
commit cb91f6656a
29 changed files with 448 additions and 115 deletions
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101
lab2CA.srcs/sources_1/new/ControlUnit.v
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@@ -3,72 +3,133 @@
module ControlUnit(
input wire [3:0] instIn,
input wire functBit,
output reg [2:0] aluOut,
output reg [3:0] aluOut,
output reg [2:0] FU,
output reg addi,
output reg mem,
output reg load,
output reg RegEn
);
output reg RegEn);
always @(instIn)begin
case(instIn)
4'b0101:
if(functBit == 1) begin
aluOut <= 3'b001; //sub
aluOut <= 4'b0001; //sub
RegEn <= 1'b0;
end
else begin
aluOut <= 3'b000; //Add
aluOut <= 4'b0000; //Add
RegEn <= 1'b0;
end
4'b0111: begin
aluOut <= 3'b111; //nor
4'b1101: begin
aluOut <= 4'b0011; //nor
RegEn <= 1'b0;
end
4'b1110:
if(functBit == 1) begin
aluOut <= 3'b100; //and
aluOut <= 4'b0100; //and
RegEn <= 1'b0;
end
else begin
aluOut <= 3'b010; //or
aluOut <= 4'b0010; //or
RegEn <= 1'b0;
end
4'b1111:
if(functBit == 1) begin
aluOut <= 3'b110; //srl
aluOut <= 4'b0110; //srl
RegEn <= 1'b0;
end
else begin
aluOut <= 3'b101; //sll
aluOut <= 4'b0101; //shift left
RegEn <= 1'b0;
end
4'b0111: begin
aluOut <= 4'b1001; //slt
RegEn <= 1'b0;
end
4'b0110: begin
addi <= 1'b1; // addi
RegEn <= 1'b0;
end
end
4'b1001: begin
FU <= 3'b010; // jump
RegEn <= 1'b1;
end
end
4'b1100: begin
FU <= 3'b011; // branch
RegEn <= 1'b1;
end
end
4'b1000: begin
FU <= 3'b001; // jumpreg
RegEn <= 1'b1;
end
end
4'b0001: begin
mem <= 1'b0; // load
RegEn <= 1'b0;
end
end
4'b0010: begin
mem <= 1'b1; // store
RegEn <= 1'b1;
end
default: aluOut <= 3'bxxxx;
end
default: aluOut <= 4'bxxxx;
endcase
end
endmodule
end
endmodule
module ControlUnit_tb();
reg [3:0] instruction;
reg functionB;
wire [3:0] aluOutput;
wire [2:0] FetchUnit;
wire addImmediate;
wire memory;
wire loadIt;
wire RegEnable;
ControlUnit ControlUnit0(
.instIn(instruction),
.functBit(functionB),
.aluOut(aluOutput),
.FU(FetchUnit),
.addi(addImmediate),
.mem(memory),
.load(loadIt),
.RegEn(RegEnable)
);
initial begin
functionB = 1'b0;
instruction = 4'b0101;
#5
functionB = 1'b1;
#5
functionB = 1'b0;
instruction = 4'b1110;
#5
functionB = 1'b1;
#5
functionB = 1'b0;
instruction = 4'b1111;
#5
functionB = 1'b1;
#5
instruction = 4'b0111;
#5
instruction = 4'b0110;
#5
instruction = 4'b1001;
#5
instruction = 4'b1100;
#5
instruction = 4'b1000;
#5
instruction = 4'b0001;
#5
instruction = 4'b0010;
#5
$finish;
end
endmodule