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Better indentation

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This commit is contained in:
WilliamMiceli
2019-04-06 16:08:02 -04:00
parent 3fb02d18e3
commit dd7a319e92
2 changed files with 12 additions and 9 deletions
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11
lab2CA.srcs/sources_1/new/FetchUnit.v
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@@ -1,9 +1,11 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
module FetchUnit(input wire clk, reset, module FetchUnit(
input wire op_idx, input wire clk, reset,
input wire [8:0] AddrIn, input wire op_idx,
output wire [8:0] AddrOut); input wire [8:0] AddrIn,
output wire [8:0] AddrOut
);
//Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a) //Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a)
wire [8:0] progC_out, result_m; wire [8:0] progC_out, result_m;
@@ -29,7 +31,6 @@ module FetchUnit(input wire clk, reset,
.out(result_m), .out(result_m),
.switch(op_idx)); .switch(op_idx));
endmodule endmodule
//testbench //testbench

10
lab2CA.srcs/sources_1/new/RegFile.v
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@@ -1,9 +1,11 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
module RegFile(input wire clk, reset, enable, module RegFile(
input wire [1:0] write_index, op0_idx, op1_idx, input wire clk, reset, enable,
input wire [8:0] write_data, input wire [1:0] write_index, op0_idx, op1_idx,
output wire [8:0] op0, op1); input wire [8:0] write_data,
output wire [8:0] op0, op1
);
wire [3:0] decOut; wire [3:0] decOut;
wire [8:0] r0_out, r1_out, r2_out, r3_out; wire [8:0] r0_out, r1_out, r2_out, r3_out;