Vivado runs/sim
This commit is contained in:
WilliamMiceli
@@ -2,8 +2,8 @@
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# Vivado v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Sat Mar 30 15:52:45 2019
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# Process ID: 9028
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# Start of session at: Sat Apr 6 14:00:40 2019
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# Process ID: 8416
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# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1
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# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
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# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
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@@ -15,9 +15,9 @@ Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 18388
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INFO: Helper process launched with PID 19172
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---------------------------------------------------------------------------------
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Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 364.258 ; gain = 100.730
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Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 362.617 ; gain = 101.777
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---------------------------------------------------------------------------------
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INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
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@@ -26,76 +26,77 @@ INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/REPOSITORIES/Education
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INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
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INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
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INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:266]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
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INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
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INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:766]
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INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:766]
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INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:396]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:401]
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INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:396]
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INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
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INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
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INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412]
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INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
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INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
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INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
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INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
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INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:325]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:331]
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INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:325]
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INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342]
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INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
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INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
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INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1300]
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INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1365]
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INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:676]
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INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:676]
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INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1365]
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INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1300]
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INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:713]
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INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:713]
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INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:632]
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INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:632]
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INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
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INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
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INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
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INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
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INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
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INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
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INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
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INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
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INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
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INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
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INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
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INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
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INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:842]
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INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:842]
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INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:916]
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INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:916]
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INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:879]
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INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:879]
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INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:309]
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INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:309]
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INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1414]
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INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1414]
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INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:524]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:530]
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INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:524]
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INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
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INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
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INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
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INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
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INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
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INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
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INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
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INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
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INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
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INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
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INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541]
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INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
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INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
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INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:13]
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INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:985]
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INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:985]
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INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:339]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:345]
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INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:339]
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INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996]
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INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996]
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INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356]
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INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
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INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (27#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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WARNING: [Synth 8-3331] design dataMemory has unconnected port address[8]
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WARNING: [Synth 8-3331] design dataMemory has unconnected port address[7]
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---------------------------------------------------------------------------------
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Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 420.883 ; gain = 157.355
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Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.656 ; gain = 157.816
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 420.883 ; gain = 157.355
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Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.656 ; gain = 157.816
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
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---------------------------------------------------------------------------------
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Loading part: xc7k160tifbg484-2L
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---------------------------------------------------------------------------------
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 420.883 ; gain = 157.355
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.656 ; gain = 157.816
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 420.883 ; gain = 157.355
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 418.656 ; gain = 157.816
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-223] decloning instance 'SE1' (sign_extend_3bit) to 'SE3'
|
||||
|
||||
@@ -114,11 +115,11 @@ Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 10
|
||||
+---RAMs :
|
||||
4K Bit RAMs := 1
|
||||
909 Bit RAMs := 1
|
||||
+---Muxes :
|
||||
7 Input 9 Bit Muxes := 1
|
||||
4 Input 9 Bit Muxes := 5
|
||||
2 Input 9 Bit Muxes := 8
|
||||
2 Input 4 Bit Muxes := 2
|
||||
4 Input 4 Bit Muxes := 2
|
||||
16 Input 4 Bit Muxes := 1
|
||||
2 Input 3 Bit Muxes := 2
|
||||
@@ -139,19 +140,16 @@ Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
4 Input 9 Bit Muxes := 1
|
||||
8 Input 2 Bit Muxes := 1
|
||||
Module instructionMemory
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
7 Input 9 Bit Muxes := 1
|
||||
Module dataMemory
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
+---RAMs :
|
||||
4K Bit RAMs := 1
|
||||
909 Bit RAMs := 1
|
||||
Module decoder
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 4 Bit Muxes := 1
|
||||
4 Input 4 Bit Muxes := 1
|
||||
Module register
|
||||
Detailed RTL Component Info :
|
||||
@@ -199,24 +197,33 @@ Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP and Shift Register Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
ROM:
|
||||
+------------------+------------+---------------+----------------+
|
||||
|Module Name | RTL Object | Depth x Width | Implemented As |
|
||||
+------------------+------------+---------------+----------------+
|
||||
|instructionMemory | p_0_out | 64x9 | LUT |
|
||||
|CPU9bits | p_0_out | 64x9 | LUT |
|
||||
+------------------+------------+---------------+----------------+
|
||||
|
||||
|
||||
Block RAM: Preliminary Mapping Report (see note below)
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|dataMemory: | memory_reg | 512 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
|
||||
|dataMemory: | memory_reg | 128 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|
||||
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished ROM, RAM, DSP and Shift Register Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6837] The timing for the instance i_1/dM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
||||
INFO: [Synth 8-6837] The timing for the instance i_0/dM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
@@ -228,7 +235,7 @@ No constraint files found.
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP and Shift Register Reporting
|
||||
@@ -238,7 +245,7 @@ Block RAM: Final Mapping Report
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|dataMemory: | memory_reg | 512 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
|
||||
|dataMemory: | memory_reg | 128 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
@@ -255,7 +262,7 @@ Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6837] The timing for the instance dM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -279,7 +286,7 @@ Start Final Netlist Cleanup
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
@@ -292,7 +299,7 @@ Report Check Netlist:
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -304,25 +311,25 @@ Report RTL Partitions:
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
@@ -339,51 +346,59 @@ Report Cell Usage:
|
||||
| |Cell |Count |
|
||||
+------+---------+------+
|
||||
|1 |BUFG | 1|
|
||||
|2 |LUT2 | 4|
|
||||
|3 |LUT3 | 3|
|
||||
|4 |LUT4 | 27|
|
||||
|5 |LUT5 | 10|
|
||||
|6 |LUT6 | 37|
|
||||
|7 |RAMB18E1 | 1|
|
||||
|8 |FDRE | 21|
|
||||
|9 |IBUF | 2|
|
||||
|10 |OBUF | 10|
|
||||
|2 |LUT2 | 13|
|
||||
|3 |LUT3 | 21|
|
||||
|4 |LUT4 | 23|
|
||||
|5 |LUT5 | 33|
|
||||
|6 |LUT6 | 135|
|
||||
|7 |MUXF7 | 11|
|
||||
|8 |RAMB18E1 | 1|
|
||||
|9 |FDRE | 81|
|
||||
|10 |IBUF | 2|
|
||||
|11 |OBUF | 10|
|
||||
+------+---------+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+-----------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-----------+------+
|
||||
|1 |top | | 116|
|
||||
|2 | FetchU |FetchUnit | 31|
|
||||
|3 | PC |register_1 | 31|
|
||||
|4 | RF |RegFile | 71|
|
||||
|5 | r0 |register | 42|
|
||||
|6 | r1 |register_0 | 29|
|
||||
|7 | dM |dataMemory | 1|
|
||||
|1 |top | | 331|
|
||||
|2 | Bank |RegFile | 45|
|
||||
|3 | r0 |register_5 | 15|
|
||||
|4 | r1 |register_6 | 9|
|
||||
|5 | r2 |register_7 | 11|
|
||||
|6 | r3 |register_8 | 10|
|
||||
|7 | FetchU |FetchUnit | 135|
|
||||
|8 | PC |register_4 | 135|
|
||||
|9 | RF |RegFile_0 | 137|
|
||||
|10 | r0 |register | 87|
|
||||
|11 | r1 |register_1 | 17|
|
||||
|12 | r2 |register_2 | 14|
|
||||
|13 | r3 |register_3 | 19|
|
||||
|14 | dM |dataMemory | 1|
|
||||
+------+---------+-----------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 2 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
|
||||
INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 684.082 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 683.707 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
73 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
72 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 684.082 ; gain = 433.695
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 684.082 ; gain = 0.000
|
||||
synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 683.707 ; gain = 435.820
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 683.707 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Sat Mar 30 15:53:22 2019...
|
||||
INFO: [Common 17-206] Exiting Vivado at Sat Apr 6 14:01:18 2019...
|
||||
|
||||
Reference in New Issue
Block a user