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Vivado runs/sim

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WilliamMiceli
2019-04-06 14:16:26 -04:00
parent b4f855c65b
commit de8740a231
65 changed files with 453 additions and 2787 deletions
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27
lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Mar 30 15:53:22 2019
| Date : Sat Apr 6 14:01:18 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
| Design : CPU9bits
@@ -30,13 +30,13 @@ Table of Contents
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 73 | 0 | 101400 | 0.07 |
| LUT as Logic | 73 | 0 | 101400 | 0.07 |
| Slice LUTs* | 193 | 0 | 101400 | 0.19 |
| LUT as Logic | 193 | 0 | 101400 | 0.19 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 21 | 0 | 202800 | 0.01 |
| Register as Flip Flop | 21 | 0 | 202800 | 0.01 |
| Slice Registers | 81 | 0 | 202800 | 0.04 |
| Register as Flip Flop | 81 | 0 | 202800 | 0.04 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
| F7 Muxes | 11 | 0 | 50700 | 0.02 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+-------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
@@ -57,7 +57,7 @@ Table of Contents
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 21 | Yes | Reset | - |
| 81 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -152,13 +152,14 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| LUT6 | 37 | LUT |
| LUT4 | 27 | LUT |
| FDRE | 21 | Flop & Latch |
| LUT6 | 135 | LUT |
| FDRE | 81 | Flop & Latch |
| LUT5 | 33 | LUT |
| LUT4 | 23 | LUT |
| LUT3 | 21 | LUT |
| LUT2 | 13 | LUT |
| MUXF7 | 11 | MuxFx |
| OBUF | 10 | IO |
| LUT5 | 10 | LUT |
| LUT2 | 4 | LUT |
| LUT3 | 3 | LUT |
| IBUF | 2 | IO |
| RAMB18E1 | 1 | Block Memory |
| BUFG | 1 | Clock |