Made testbench

This commit is contained in:
WilliamMiceli
2019-03-16 13:02:29 -04:00
parent c988ddb899
commit ef8b9c92e5

View File

@@ -969,6 +969,29 @@ module sign_extend_2bit(
endmodule
//testbench
module sign_extend_2bit_tb();
reg [1:0] A;
wire [8:0] B;
sign_extend_2bit tb0(
.A(A),
.B(B));
initial begin
A = 2'b00;
#5
A = 2'b01;
#5
A = 2'b10;
#5
A = 2'b11;
#5
$finish;
end
endmodule
module sub_9bit(
input wire [8:0] A,
input wire [8:0] B,