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Johannes
2019-04-06 13:16:35 -04:00
parent 2746d6d49c 443d01eba1
commit f34b3d4098
81 changed files with 3467 additions and 1777 deletions
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4
README.md
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@@ -1,5 +1,5 @@
# ECE 3570 Lab
## Unknown Status of Fixes
## Things to fix
* Only two registers are being written to, first two within simulation is not being written to
* Get programs working properly

96
lab2CA.cache/wt/webtalk_pa.xml
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@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Sun Mar 24 19:55:45 2019">
<application name="pa" timeStamp="Sat Mar 30 15:58:21 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="88e779ed22f94d2db93b335d17c75f15" type="ProjectID"/>
<property name="ProjectIteration" value="21" type="ProjectIteration"/>
<property name="ProjectIteration" value="25" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
@@ -17,7 +17,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="CloseProject" value="17" type="JavaHandler"/>
<property name="CloseProject" value="19" type="JavaHandler"/>
<property name="EditDelete" value="2" type="JavaHandler"/>
<property name="FlipToViewTaskRTLAnalysis" value="1" type="JavaHandler"/>
<property name="OpenDesign" value="1" type="JavaHandler"/>
@@ -25,15 +25,16 @@ This means code written to parse this file will need to be revisited each subseq
<property name="OpenProject" value="3" type="JavaHandler"/>
<property name="ReloadDesign" value="1" type="JavaHandler"/>
<property name="ReportTimingSummary" value="9" type="JavaHandler"/>
<property name="RunImplementation" value="26" type="JavaHandler"/>
<property name="RunSchematic" value="27" type="JavaHandler"/>
<property name="RunSynthesis" value="20" type="JavaHandler"/>
<property name="RunImplementation" value="30" type="JavaHandler"/>
<property name="RunSchematic" value="30" type="JavaHandler"/>
<property name="RunSynthesis" value="29" type="JavaHandler"/>
<property name="SaveFileProxyHandler" value="2" type="JavaHandler"/>
<property name="SaveLayoutAs" value="1" type="JavaHandler"/>
<property name="SetSourceEnabled" value="2" type="JavaHandler"/>
<property name="SetTopNode" value="38" type="JavaHandler"/>
<property name="SetSourceEnabled" value="5" type="JavaHandler"/>
<property name="SetTopNode" value="42" type="JavaHandler"/>
<property name="ShowSimulationDefaultWaveFormView" value="1" type="JavaHandler"/>
<property name="ShowView" value="13" type="JavaHandler"/>
<property name="ShowSource" value="1" type="JavaHandler"/>
<property name="ShowView" value="18" type="JavaHandler"/>
<property name="SimulationClose" value="6" type="JavaHandler"/>
<property name="SimulationRelaunch" value="90" type="JavaHandler"/>
<property name="SimulationRun" value="95" type="JavaHandler"/>
@@ -42,10 +43,10 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ToggleViewNavigator" value="1" type="JavaHandler"/>
<property name="ToolsSettings" value="2" type="JavaHandler"/>
<property name="UpdateSourceFiles" value="1" type="JavaHandler"/>
<property name="ViewLayoutCmd" value="3" type="JavaHandler"/>
<property name="ViewTaskImplementation" value="2" type="JavaHandler"/>
<property name="ViewLayoutCmd" value="2" type="JavaHandler"/>
<property name="ViewTaskImplementation" value="4" type="JavaHandler"/>
<property name="ViewTaskProjectManager" value="1" type="JavaHandler"/>
<property name="ViewTaskRTLAnalysis" value="13" type="JavaHandler"/>
<property name="ViewTaskRTLAnalysis" value="15" type="JavaHandler"/>
<property name="WaveformOpenConfiguration" value="1" type="JavaHandler"/>
<property name="WaveformSaveConfiguration" value="9" type="JavaHandler"/>
<property name="WaveformSaveConfigurationAs" value="1" type="JavaHandler"/>
@@ -58,20 +59,21 @@ This means code written to parse this file will need to be revisited each subseq
<property name="BaseDialogUtils_OPEN_IN_SPECIFIED_LAYOUT" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_APPLY" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="31" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="131" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="134" type="GuiHandlerData"/>
<property name="BaseDialog_YES" value="20" type="GuiHandlerData"/>
<property name="ClosePlanner_YES" value="1" type="GuiHandlerData"/>
<property name="CmdMsgDialog_MESSAGES" value="2" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="13" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="2" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="433" type="GuiHandlerData"/>
<property name="CodeView_TOGGLE_COLUMN_SELECTION_MODE" value="14" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="531" type="GuiHandlerData"/>
<property name="FloatingTopDialog_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="12" type="GuiHandlerData"/>
<property name="FloatingTopDialog_SPECIFY_NEW_TOP_MODULE" value="10" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="255" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="279" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="70" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="60" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="44" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="67" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="47" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="35" type="GuiHandlerData"/>
<property name="HCodeEditor_BLANK_OPERATIONS" value="6" type="GuiHandlerData"/>
<property name="HCodeEditor_CLOSE" value="9" type="GuiHandlerData"/>
<property name="HCodeEditor_COMMANDS_TO_FOLD_TEXT" value="3" type="GuiHandlerData"/>
@@ -80,18 +82,18 @@ This means code written to parse this file will need to be revisited each subseq
<property name="HInputHandler_INDENT_SELECTION" value="1" type="GuiHandlerData"/>
<property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="15" type="GuiHandlerData"/>
<property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/>
<property name="InstanceMenu_FLOORPLANNING" value="1" type="GuiHandlerData"/>
<property name="InstanceMenu_FLOORPLANNING" value="2" type="GuiHandlerData"/>
<property name="LaunchPanel_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_CHECKPOINT" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_CONSTRAINTS" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="10" type="GuiHandlerData"/>
<property name="MainMenuMgr_EXPORT" value="5" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="54" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="60" type="GuiHandlerData"/>
<property name="MainMenuMgr_FLOW" value="8" type="GuiHandlerData"/>
<property name="MainMenuMgr_IP" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_BLOCK_DESIGN" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="28" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="30" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORTS" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_RUN" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_SETTINGS" value="2" type="GuiHandlerData"/>
@@ -102,28 +104,29 @@ This means code written to parse this file will need to be revisited each subseq
<property name="MainMenuMgr_WINDOW" value="8" type="GuiHandlerData"/>
<property name="MainToolbarMgr_RUN" value="2" type="GuiHandlerData"/>
<property name="MainWinMenuMgr_LAYOUT" value="4" type="GuiHandlerData"/>
<property name="MainWinToolbarMgr_SELECT_OR_SAVE_WINDOW_LAYOUT" value="4" type="GuiHandlerData"/>
<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="4" type="GuiHandlerData"/>
<property name="MainWinToolbarMgr_SELECT_OR_SAVE_WINDOW_LAYOUT" value="3" type="GuiHandlerData"/>
<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="6" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_SEVERITY" value="2" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="131" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="153" type="GuiHandlerData"/>
<property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="5" type="GuiHandlerData"/>
<property name="MsgView_WARNING_MESSAGES" value="3" type="GuiHandlerData"/>
<property name="NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE" value="116" type="GuiHandlerData"/>
<property name="NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE" value="117" type="GuiHandlerData"/>
<property name="NetlistSchMenuAndMouse_EXPAND_COLLAPSE" value="1" type="GuiHandlerData"/>
<property name="NetlistSchMenuAndMouse_VIEW" value="2" type="GuiHandlerData"/>
<property name="NetlistSchematicView_SHOW_IO_PORTS_IN_THIS_SCHEMATIC" value="1" type="GuiHandlerData"/>
<property name="NetlistTreeView_NETLIST_TREE" value="4" type="GuiHandlerData"/>
<property name="OpenFileAction_CANCEL" value="2" type="GuiHandlerData"/>
<property name="OpenFileAction_OK" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="42" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="16" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="51" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="18" type="GuiHandlerData"/>
<property name="PACommandNames_GOTO_INSTANTIATION" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_MESSAGE_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_RTL_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_RELOAD_RTL_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SCHEMATIC" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SELECT_AREA" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_SET_AS_TOP" value="39" type="GuiHandlerData"/>
<property name="PACommandNames_SET_AS_TOP" value="43" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_CLOSE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_DEFAULT_WAVEFORM_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RELAUNCH" value="97" type="GuiHandlerData"/>
@@ -132,16 +135,17 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_FUNCTIONAL" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_TIMING" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_SETTINGS" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_SRC_ENABLE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SRC_DISABLE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SRC_ENABLE" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_SRC_REPLACE_FILE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_TOGGLE_VIEW_NAV" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_FIT" value="10" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_OUT" value="3" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="34" type="GuiHandlerData"/>
<property name="PAViews_DEVICE" value="1" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="44" type="GuiHandlerData"/>
<property name="PAViews_DEVICE" value="3" type="GuiHandlerData"/>
<property name="PAViews_PATH_TABLE" value="1" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="65" type="GuiHandlerData"/>
<property name="PAViews_SCHEMATIC" value="23" type="GuiHandlerData"/>
<property name="PAViews_SCHEMATIC" value="28" type="GuiHandlerData"/>
<property name="PathReportTableView_DESCRIPTION" value="2" type="GuiHandlerData"/>
<property name="PlanAheadTab_SHOW_FLOW_NAVIGATOR" value="2" type="GuiHandlerData"/>
<property name="PowerResultTab_REPORT_NAVIGATION_TREE" value="1" type="GuiHandlerData"/>
@@ -149,46 +153,48 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ProgressDialog_BACKGROUND" value="7" type="GuiHandlerData"/>
<property name="ProgressDialog_CANCEL" value="5" type="GuiHandlerData"/>
<property name="ProjectSettingsSimulationPanel_TABBED_PANE" value="2" type="GuiHandlerData"/>
<property name="ProjectTab_RELOAD" value="23" type="GuiHandlerData"/>
<property name="ProjectTab_RELOAD" value="27" type="GuiHandlerData"/>
<property name="RDICommands_COPY" value="2" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
<property name="RDICommands_LINE_COMMENT" value="2" type="GuiHandlerData"/>
<property name="RDICommands_REDO" value="1" type="GuiHandlerData"/>
<property name="RDICommands_SAVE_FILE" value="122" type="GuiHandlerData"/>
<property name="RDICommands_SAVE_FILE" value="121" type="GuiHandlerData"/>
<property name="RDICommands_WAVEFORM_OPEN_CONFIGURATION" value="1" type="GuiHandlerData"/>
<property name="RDICommands_WAVEFORM_SAVE_CONFIGURATION" value="5" type="GuiHandlerData"/>
<property name="RDICommands_WAVEFORM_SAVE_CONFIGURATION_AS" value="1" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="921" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="874" type="GuiHandlerData"/>
<property name="ReportTimingSummaryDialog_REPORT_TIMING_SUMMARY_DIALOG_TABBED" value="14" type="GuiHandlerData"/>
<property name="ReportTimingSummaryDialog_REPORT_UNCONSTRAINED_PATHS" value="6" type="GuiHandlerData"/>
<property name="RunGadget_SHOW_ERROR" value="1" type="GuiHandlerData"/>
<property name="RunGadget_SHOW_WARNING_AND_ERROR_MESSAGES_IN_MESSAGES" value="4" type="GuiHandlerData"/>
<property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_SAVE" value="12" type="GuiHandlerData"/>
<property name="SelectMenu_HIGHLIGHT" value="1" type="GuiHandlerData"/>
<property name="SelectMenu_MARK" value="1" type="GuiHandlerData"/>
<property name="SelectMenu_HIGHLIGHT" value="2" type="GuiHandlerData"/>
<property name="SelectMenu_MARK" value="2" type="GuiHandlerData"/>
<property name="SelectTopModuleDialog_SELECT_TOP_MODULE" value="12" type="GuiHandlerData"/>
<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="82" type="GuiHandlerData"/>
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="141" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="42" type="GuiHandlerData"/>
<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="80" type="GuiHandlerData"/>
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="140" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="50" type="GuiHandlerData"/>
<property name="StaleMoreAction_OUT_OF_DATE_DETAILS" value="1" type="GuiHandlerData"/>
<property name="StaleRunDialog_NO" value="3" type="GuiHandlerData"/>
<property name="StaleRunDialog_YES" value="1" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="26" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="30" type="GuiHandlerData"/>
<property name="SyntheticaStateMonitor_CANCEL" value="2" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="37" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="41" type="GuiHandlerData"/>
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiHandlerData"/>
<property name="TclFindDialog_RESULT_NAME" value="2" type="GuiHandlerData"/>
<property name="TimingDialogUtils_RESULTS_NAME" value="1" type="GuiHandlerData"/>
<property name="TimingItemFlatTablePanel_TABLE" value="3" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="503" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="487" type="GuiHandlerData"/>
<property name="WaveformView_GOTO_CURSOR" value="3" type="GuiHandlerData"/>
<property name="WaveformView_GOTO_LAST_TIME" value="1" type="GuiHandlerData"/>
<property name="WaveformView_GOTO_TIME_0" value="8" type="GuiHandlerData"/>
<property name="WaveformView_PREVIOUS_MARKER" value="1" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="18" type="GuiMode"/>
<property name="GuiMode" value="69" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="16" type="TclMode"/>
<property name="TclMode" value="67" type="TclMode"/>
</item>
</section>
</application>

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lab2CA.runs/.jobs/vrs_config_45.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_46.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_47.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_48.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_49.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_50.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_51.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_52.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_53.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_54.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_55.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_56.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_57.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

152
lab2CA.runs/impl_1/CPU9bits.tcl Normal file
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#
# Report generation script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
proc start_step { step } {
set stopFile ".stop.rst"
if {[file isfile .stop.rst]} {
puts ""
puts "*** Halting run - EA reset detected ***"
puts ""
puts ""
return -code error
}
set beginFile ".$step.begin.rst"
set platform "$::tcl_platform(platform)"
set user "$::tcl_platform(user)"
set pid [pid]
set host ""
if { [string equal $platform unix] } {
if { [info exist ::env(HOSTNAME)] } {
set host $::env(HOSTNAME)
}
} else {
if { [info exist ::env(COMPUTERNAME)] } {
set host $::env(COMPUTERNAME)
}
}
set ch [open $beginFile w]
puts $ch "<?xml version=\"1.0\"?>"
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
puts $ch " </Process>"
puts $ch "</ProcessHandle>"
close $ch
}
proc end_step { step } {
set endFile ".$step.end.rst"
set ch [open $endFile w]
close $ch
}
proc step_failed { step } {
set endFile ".$step.error.rst"
set ch [open $endFile w]
close $ch
}
set_msg_config -id {Synth 8-256} -limit 10000
set_msg_config -id {Synth 8-638} -limit 10000
start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
create_project -in_memory -part xc7k160tifbg484-2L
set_property design_mode GateLvl [current_fileset]
set_param project.singleFileAddWarning.threshold 0
set_property webtalk.parent_dir {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/wt} [current_project]
set_property parent.project_path {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr} [current_project]
set_property ip_output_repo {{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/ip}} [current_project]
set_property ip_cache_permissions {read write} [current_project]
add_files -quiet {{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp}}
link_design -top CPU9bits -part xc7k160tifbg484-2L
close_msg_db -file init_design.pb
} RESULT]
if {$rc} {
step_failed init_design
return -code error $RESULT
} else {
end_step init_design
unset ACTIVE_STEP
}
start_step opt_design
set ACTIVE_STEP opt_design
set rc [catch {
create_msg_db opt_design.pb
opt_design
write_checkpoint -force CPU9bits_opt.dcp
create_report "impl_1_opt_report_drc_0" "report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx"
close_msg_db -file opt_design.pb
} RESULT]
if {$rc} {
step_failed opt_design
return -code error $RESULT
} else {
end_step opt_design
unset ACTIVE_STEP
}
start_step place_design
set ACTIVE_STEP place_design
set rc [catch {
create_msg_db place_design.pb
if { [llength [get_debug_cores -quiet] ] > 0 } {
implement_debug_core
}
place_design
write_checkpoint -force CPU9bits_placed.dcp
create_report "impl_1_place_report_io_0" "report_io -file CPU9bits_io_placed.rpt"
create_report "impl_1_place_report_utilization_0" "report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb"
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt"
close_msg_db -file place_design.pb
} RESULT]
if {$rc} {
step_failed place_design
return -code error $RESULT
} else {
end_step place_design
unset ACTIVE_STEP
}
start_step route_design
set ACTIVE_STEP route_design
set rc [catch {
create_msg_db route_design.pb
route_design
write_checkpoint -force CPU9bits_routed.dcp
create_report "impl_1_route_report_drc_0" "report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx"
create_report "impl_1_route_report_methodology_0" "report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx"
create_report "impl_1_route_report_power_0" "report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx"
create_report "impl_1_route_report_route_status_0" "report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb"
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation "
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file CPU9bits_incremental_reuse_routed.rpt"
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt"
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx"
close_msg_db -file route_design.pb
} RESULT]
if {$rc} {
write_checkpoint -force CPU9bits_routed_error.dcp
step_failed route_design
return -code error $RESULT
} else {
end_step route_design
unset ACTIVE_STEP
}

473
lab2CA.runs/impl_1/CPU9bits.vdi Normal file
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#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Mar 30 15:53:31 2019
# Process ID: 13696
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits.vdi
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source CPU9bits.tcl -notrace
Command: link_design -top CPU9bits -part xc7k160tifbg484-2L
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
INFO: [Project 1-570] Preparing netlist for logic optimization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 581.816 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 587.391 ; gain = 332.746
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 603.059 ; gain = 15.668
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 257e1e38
Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1127.293 ; gain = 524.234
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 257e1e38
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 1225.961 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 257e1e38
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 1225.961 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 257e1e38
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.083 . Memory (MB): peak = 1225.961 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 257e1e38
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.093 . Memory (MB): peak = 1225.961 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 257e1e38
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.196 . Memory (MB): peak = 1225.961 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 257e1e38
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.199 . Memory (MB): peak = 1225.961 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 0 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1225.961 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 257e1e38
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.206 . Memory (MB): peak = 1225.961 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.000 | TNS=0.000 |
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 1 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 2
Ending PowerOpt Patch Enables Task | Checksum: 257e1e38
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1335.719 ; gain = 0.000
Ending Power Optimization Task | Checksum: 257e1e38
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1335.719 ; gain = 109.758
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 257e1e38
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1335.719 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 257e1e38
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1335.719 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
28 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1335.719 ; gain = 748.328
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
Command: report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1e0025bd
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1335.719 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: be8e8081
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 154227d99
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 154227d99
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 154227d99
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 154227d99
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
Phase 2 Global Placement | Checksum: 168f30526
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 168f30526
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 10b26ca05
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 171e1f517
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 171e1f517
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: eb242549
Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: eb242549
Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: eb242549
Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 3 Detail Placement | Checksum: eb242549
Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: eb242549
Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: eb242549
Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: eb242549
Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: eb242549
Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up | Checksum: eb242549
Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Ending Placer Task | Checksum: 99ceed10
Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
45 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1335.719 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.323 . Memory (MB): peak = 1335.719 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file CPU9bits_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.130 . Memory (MB): peak = 1335.719 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1335.719 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 7bcec753 ConstDB: 0 ShapeSum: 1e0025bd RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 16c615449
Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1486.191 ; gain = 150.473
Post Restoration Checksum: NetGraph: 8cbcc684 NumContArr: dfa48dc5 Constraints: 0 Timing: 0
Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 16c615449
Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1490.352 ; gain = 154.633
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 16c615449
Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1490.352 ; gain = 154.633
Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: 10053be5d
Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1517.723 ; gain = 182.004
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 94ab7af4
Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 15
Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: ab64b9a3
Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Phase 4 Rip-up And Reroute | Checksum: ab64b9a3
Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: ab64b9a3
Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: ab64b9a3
Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Phase 6 Post Hold Fix | Checksum: ab64b9a3
Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.00626714 %
Global Horizontal Routing Utilization = 0.0102302 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Congestion Report
North Dir 1x1 Area, Max Cong = 18.9189%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 10.8108%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 22.0588%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 27.9412%, No Congested Regions.
------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: ab64b9a3
Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: ab64b9a3
Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 148b7f565
Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
57 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:56 ; elapsed = 00:00:42 . Memory (MB): peak = 1517.723 ; gain = 182.004
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1517.723 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 1517.723 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
Command: report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
Command: report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
Command: report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
68 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
INFO: [runtcl-4] Executing : report_incremental_reuse -file CPU9bits_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Sat Mar 30 15:55:20 2019...

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Mar 30 15:55:20 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Command : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx
| Design : CPU9bits
| Device : 7k160ti-fbg484
| Speed File : -2L PRODUCTION 1.12 2017-02-17
---------------------------------------------------------------------------------------------------------------------------------------------------------
Bus Skew Report
No bus skew constraints

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Mar 30 15:55:20 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Command : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt
| Design : CPU9bits
| Device : 7k160ti-fbg484
| Speed File : -2L PRODUCTION 1.12 2017-02-17
| Temperature Grade : I
-------------------------------------------------------------------------------------------
Clock Utilization Report
Table of Contents
-----------------
1. Clock Primitive Utilization
2. Global Clock Resources
3. Global Clock Source Details
4. Clock Regions: Key Resource Utilization
5. Clock Regions : Global Clock Summary
6. Device Cell Placement Summary for Global Clock g0
7. Clock Region Cell Placement per Global Clock: Region X0Y1
1. Clock Primitive Utilization
------------------------------
+----------+------+-----------+-----+--------------+--------+
| Type | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL | 1 | 32 | 0 | 0 | 0 |
| BUFH | 0 | 120 | 0 | 0 | 0 |
| BUFIO | 0 | 32 | 0 | 0 | 0 |
| BUFMR | 0 | 16 | 0 | 0 | 0 |
| BUFR | 0 | 32 | 0 | 0 | 0 |
| MMCM | 0 | 8 | 0 | 0 | 0 |
| PLL | 0 | 8 | 0 | 0 | 0 |
+----------+------+-----------+-----+--------------+--------+
2. Global Clock Resources
-------------------------
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 22 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
3. Global Clock Source Details
------------------------------
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
| src0 | g0 | IBUF/O | None | IOB_X0Y78 | X0Y1 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF |
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
4. Clock Regions: Key Resource Utilization
------------------------------------------
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 21 | 2800 | 14 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 2150 | 0 | 800 | 0 | 50 | 0 | 25 | 0 | 60 |
| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y4 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2300 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts
5. Clock Regions : Global Clock Summary
---------------------------------------
All Modules
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y4 | 0 | 0 |
| Y3 | 0 | 0 |
| Y2 | 0 | 0 |
| Y1 | 1 | 0 |
| Y0 | 0 | 0 |
+----+----+----+
6. Device Cell Placement Summary for Global Clock g0
----------------------------------------------------
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
| g0 | BUFG/O | n/a | | | | 22 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+-----+----+
| | X0 | X1 |
+----+-----+----+
| Y4 | 0 | 0 |
| Y3 | 0 | 0 |
| Y2 | 0 | 0 |
| Y1 | 22 | 0 |
| Y0 | 0 | 0 |
+----+-----+----+
7. Clock Region Cell Placement per Global Clock: Region X0Y1
------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
| g0 | n/a | BUFG/O | None | 22 | 0 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
# Location of BUFG Primitives
set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst]
# Location of IO Primitives which is load of clock spine
# Location of clock ports
set_property LOC IOB_X0Y78 [get_ports clk]
# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0"
#startgroup
create_pblock {CLKAG_clk_IBUF_BUFG}
add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]]
resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1}
#endgroup

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Mar 30 15:54:32 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Command : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
| Design : CPU9bits
| Device : xc7k160ti
-------------------------------------------------------------------------------------
Control Set Information
Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information
1. Summary
----------
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets | 3 |
| Unused register locations in slices containing registers | 19 |
+----------------------------------------------------------+-------+
2. Histogram
------------
+--------+--------------+
| Fanout | Control Sets |
+--------+--------------+
| 3 | 1 |
| 9 | 2 |
+--------+--------------+
3. Flip-Flop Distribution
-------------------------
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 3 | 1 |
| No | No | Yes | 0 | 0 |
| No | Yes | No | 0 | 0 |
| Yes | No | No | 0 | 0 |
| Yes | No | Yes | 0 | 0 |
| Yes | Yes | No | 18 | 8 |
+--------------+-----------------------+------------------------+-----------------+--------------+
4. Detailed Control Set Information
-----------------------------------
+----------------+----------------------------+------------------+------------------+----------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+----------------+----------------------------+------------------+------------------+----------------+
| clk_IBUF_BUFG | | | 1 | 3 |
| clk_IBUF_BUFG | FetchU/PC/E[0] | reset_IBUF | 4 | 9 |
| clk_IBUF_BUFG | FetchU/PC/Dout_reg[0]_1[0] | reset_IBUF | 4 | 9 |
+----------------+----------------------------+------------------+------------------+----------------+

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Mar 30 15:54:22 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Command : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
| Design : CPU9bits
| Device : xc7k160tifbg484-2L
| Speed File : -2L
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 3
+----------+------------------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+------------------+-----------------------------------------------------+------------+
| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 |
| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 |
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
+----------+------------------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
NSTD-1#1 Critical Warning
Unspecified I/O Standard
12 out of 12 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset.
Related violations: <none>
UCIO-1#1 Critical Warning
Unconstrained Logical Port
12 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset.
Related violations: <none>
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Mar 30 15:55:17 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Command : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
| Design : CPU9bits
| Device : xc7k160tifbg484-2L
| Speed File : -2L
| Design State : Fully Routed
------------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 3
+----------+------------------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+------------------+-----------------------------------------------------+------------+
| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 |
| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 |
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
+----------+------------------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
NSTD-1#1 Critical Warning
Unspecified I/O Standard
12 out of 12 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset.
Related violations: <none>
UCIO-1#1 Critical Warning
Unconstrained Logical Port
12 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset.
Related violations: <none>
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>

526
lab2CA.runs/impl_1/CPU9bits_io_placed.rpt Normal file
View File

@@ -0,0 +1,526 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Mar 30 15:54:32 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Command : report_io -file CPU9bits_io_placed.rpt
| Design : CPU9bits
| Device : xc7k160ti
| Speed File : -2L
| Package : fbg484
| Package Version : FINAL 2012-06-26
| Package Pin Delay Version : VERS. 2.0 2012-06-26
-------------------------------------------------------------------------------------------------
IO Information
Table of Contents
-----------------
1. Summary
2. IO Assignments by Package Pin
1. Summary
----------
+---------------+
| Total User IO |
+---------------+
| 12 |
+---------------+
2. IO Assignments by Package Pin
--------------------------------
+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| A3 | | | MGTXTXN3_115 | Gigabit | | | | | | | | | | | | | | | |
| A4 | | | MGTXTXP3_115 | Gigabit | | | | | | | | | | | | | | | |
| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A8 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| A9 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| A10 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| A11 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A13 | | High Range | IO_L4P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
| A14 | | High Range | IO_L4N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A15 | | High Range | IO_L9N_T1_DQS_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A16 | | High Range | IO_L8N_T1_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| A18 | | High Range | IO_L10N_T1_AD4N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A19 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | |
| A20 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
| A21 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA1 | | High Performance | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA3 | | High Performance | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AA4 | | High Performance | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AA5 | | High Performance | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA6 | | High Performance | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA7 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| AA8 | | High Performance | IO_L5N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA9 | | High Performance | IO_L5P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA10 | | High Performance | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA11 | | High Performance | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA13 | | High Performance | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA14 | | High Range | IO_L18P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA15 | | High Range | IO_L18N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA16 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| AA18 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA19 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA20 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA21 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB1 | | High Performance | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AB2 | | High Performance | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AB3 | | High Performance | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AB4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| AB5 | | High Performance | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB6 | | High Performance | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB7 | | High Performance | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB8 | | High Performance | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB10 | | High Performance | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB11 | | High Performance | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB12 | | High Performance | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB13 | | High Performance | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| AB15 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB16 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB17 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB18 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB20 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB21 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB22 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| B1 | | | MGTXTXN2_115 | Gigabit | | | | | | | | | | | | | | | |
| B2 | | | MGTXTXP2_115 | Gigabit | | | | | | | | | | | | | | | |
| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B5 | | | MGTXRXN3_115 | Gigabit | | | | | | | | | | | | | | | |
| B6 | | | MGTXRXP3_115 | Gigabit | | | | | | | | | | | | | | | |
| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B8 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| B9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B10 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| B11 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| B12 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
| B13 | | High Range | IO_L5N_T0_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
| B14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| B15 | | High Range | IO_L9P_T1_DQS_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
| B16 | | High Range | IO_L8P_T1_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
| B17 | | High Range | IO_L10P_T1_AD4P_15 | User IO | | 15 | | | | | | | | | | | | | |
| B18 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | |
| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B20 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
| B21 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
| B22 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
| C1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| C3 | | | MGTXRXN2_115 | Gigabit | | | | | | | | | | | | | | | |
| C4 | | | MGTXRXP2_115 | Gigabit | | | | | | | | | | | | | | | |
| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| C7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C8 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| C9 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
| C10 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| C11 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| C12 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C13 | | High Range | IO_L5P_T0_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C14 | | High Range | IO_L7P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C15 | | High Range | IO_L7N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C17 | | High Range | IO_L12P_T1_MRCC_AD5P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C18 | | High Range | IO_L12N_T1_MRCC_AD5N_15 | User IO | | 15 | | | | | | | | | | | | | |
| C19 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | |
| C20 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
| C21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| C22 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
| D1 | | | MGTXTXN1_115 | Gigabit | | | | | | | | | | | | | | | |
| D2 | | | MGTXTXP1_115 | Gigabit | | | | | | | | | | | | | | | |
| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D5 | | | MGTREFCLK0N_115 | Gigabit | | | | | | | | | | | | | | | |
| D6 | | | MGTREFCLK0P_115 | Gigabit | | | | | | | | | | | | | | | |
| D7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D8 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| D9 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| D10 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| D11 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| D12 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | |
| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D14 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
| D15 | | High Range | IO_L11P_T1_SRCC_AD12P_15 | User IO | | 15 | | | | | | | | | | | | | |
| D16 | | High Range | IO_L11N_T1_SRCC_AD12N_15 | User IO | | 15 | | | | | | | | | | | | | |
| D17 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| D18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| D19 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | |
| D20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | |
| D21 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| D22 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| E1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| E3 | | | MGTXRXN1_115 | Gigabit | | | | | | | | | | | | | | | |
| E4 | | | MGTXRXP1_115 | Gigabit | | | | | | | | | | | | | | | |
| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E8 | | High Range | IO_24_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| E9 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E11 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| E12 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| E13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| E14 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| E15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| E16 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| E17 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| E18 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| E19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | |
| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E21 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | |
| E22 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
| F1 | | | MGTXTXN0_115 | Gigabit | | | | | | | | | | | | | | | |
| F2 | | | MGTXTXP0_115 | Gigabit | | | | | | | | | | | | | | | |
| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F5 | | | MGTREFCLK1N_115 | Gigabit | | | | | | | | | | | | | | | |
| F6 | | | MGTREFCLK1P_115 | Gigabit | | | | | | | | | | | | | | | |
| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F8 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| F9 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| F10 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| F11 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| F12 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| F13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| F14 | | High Range | IO_6_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
| F15 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
| F16 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | |
| F19 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
| F20 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
| F21 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
| F22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| G3 | | | MGTXRXN0_115 | Gigabit | | | | | | | | | | | | | | | |
| G4 | | | MGTXRXP0_115 | Gigabit | | | | | | | | | | | | | | | |
| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| G7 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
| G8 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| G9 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| G10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| G11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| G12 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| G13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G15 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
| G16 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
| G17 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| G18 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
| G19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| G20 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
| G21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
| G22 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
| H1 | | | MGTAVTTRCAL_115 | Gigabit | | | | | | | | | | | | | | | |
| H2 | | | MGTRREF_115 | Gigabit | | | | | | | | | | | | | | | |
| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H6 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
| H7 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
| H8 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| H9 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| H10 | | High Range | IO_18_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H12 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| H13 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| H14 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| H15 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | |
| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| H17 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
| H18 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
| H19 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
| H20 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H22 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | |
| J1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J4 | | | MGTVCCAUX | Gigabit Power | | | | | | | | | | | | | | | |
| J5 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
| J6 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
| J7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J16 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | |
| J17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | |
| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J19 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
| J20 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| J21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
| J22 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | |
| K1 | | High Performance | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K2 | | High Performance | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K3 | | High Performance | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K4 | | High Performance | IO_0_VRN_34 | User IO | | 34 | | | | | | | | | | | | | |
| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
| K7 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| K9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| K11 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| K12 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K16 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
| K17 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
| K18 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| K19 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
| K20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| K21 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| K22 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
| L1 | | High Performance | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L3 | | High Performance | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L4 | | High Performance | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
| L5 | | High Performance | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L6 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
| L7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L11 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
| L12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
| L13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| L14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L16 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| L18 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
| L19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| L20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| L21 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | |
| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M1 | | High Performance | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| M2 | | High Performance | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| M3 | | High Performance | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| M4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| M5 | | High Performance | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| M6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
| M7 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| M11 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
| M12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M16 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
| M17 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| M18 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M20 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
| M21 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | |
| M22 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| N1 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| N2 | | High Performance | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| N3 | | High Performance | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| N4 | | High Performance | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| N5 | | High Performance | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| N12 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| N13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N17 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | |
| N18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| N19 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| N20 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | |
| N21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| N22 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| P1 | | High Performance | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| P2 | | High Performance | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P4 | | High Performance | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| P5 | | High Performance | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| P6 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
| P7 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
| P8 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| P15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P16 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | |
| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| P19 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | |
| P20 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | |
| P21 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | |
| P22 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | |
| R1 | | High Performance | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| R2 | | High Performance | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| R3 | | High Performance | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| R4 | | High Performance | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| R5 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| R6 | | High Performance | IO_L8N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| R7 | | High Performance | IO_L8P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| R16 | reset | High Range | IO_L20P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
| R17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
| R18 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
| R19 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R21 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | |
| R22 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | |
| T1 | | High Performance | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| T2 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| T3 | | High Performance | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| T4 | | High Performance | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| T5 | | High Performance | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| T6 | | High Performance | IO_0_VRN_33 | User IO | | 33 | | | | | | | | | | | | | |
| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T8 | | High Performance | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| T9 | | High Performance | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| T10 | | High Performance | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| T11 | | High Performance | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| T12 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| T13 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| T14 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | |
| T15 | result[2] | High Range | IO_L24P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| T16 | done | High Range | IO_L20N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T18 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| T19 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | |
| T20 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| T21 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| T22 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| U1 | | High Performance | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| U2 | | High Performance | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| U3 | | High Performance | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U5 | | High Performance | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| U6 | | High Performance | IO_L10N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| U7 | | High Performance | IO_L10P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| U8 | | High Performance | IO_L9P_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| U9 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| U10 | | High Performance | IO_L14P_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| U11 | | High Performance | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| U12 | | High Performance | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| U13 | | High Performance | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U15 | result[1] | High Range | IO_L24N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| U16 | | High Range | IO_L19P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| U17 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| U18 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| U19 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| U20 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
| U21 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| U22 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V2 | | High Performance | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| V3 | | High Performance | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| V4 | | High Performance | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| V5 | | High Performance | IO_25_VRP_34 | User IO | | 34 | | | | | | | | | | | | | |
| V6 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| V7 | | High Performance | IO_L11P_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| V8 | | High Performance | IO_L9N_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| V9 | | High Performance | IO_L14N_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| V10 | | High Performance | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V12 | | High Performance | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| V13 | | High Performance | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| V14 | result[0] | High Range | IO_25_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| V15 | result[4] | High Range | IO_L23P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| V17 | | High Range | IO_L19N_T3_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
| V18 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| V19 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| V20 | clk | High Range | IO_L11P_T1_SRCC_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V22 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| W1 | | High Performance | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| W2 | | High Performance | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| W3 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| W4 | | High Performance | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| W5 | | High Performance | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| W6 | | High Performance | IO_L7P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| W7 | | High Performance | IO_L11N_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W9 | | High Performance | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| W10 | | High Performance | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| W11 | | High Performance | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W12 | | High Performance | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| W13 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| W14 | result[6] | High Range | IO_L22P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| W15 | result[3] | High Range | IO_L23N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| W16 | result[8] | High Range | IO_L21P_T3_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| W17 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W19 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| W20 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| W21 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| W22 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y1 | | High Performance | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| Y2 | | High Performance | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| Y3 | | High Performance | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| Y4 | | High Performance | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y6 | | High Performance | IO_L7N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y7 | | High Performance | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y8 | | High Performance | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y9 | | High Performance | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y10 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| Y11 | | High Performance | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y12 | | High Performance | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y13 | | High Performance | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y14 | result[5] | High Range | IO_L22N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y16 | result[7] | High Range | IO_L21N_T3_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| Y17 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y18 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y19 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y20 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| Y21 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y22 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
* Default value
** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Mar 30 15:55:19 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Command : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
| Design : CPU9bits
| Device : xc7k160tifbg484-2L
| Speed File : -2L
| Design State : Fully Routed
--------------------------------------------------------------------------------------------------------------------------------------------------------------
Report Methodology
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Max violations: <unlimited>
Violations found: 22
+-----------+----------+-----------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+----------+-----------------------------+------------+
| TIMING-17 | Warning | Non-clocked sequential cell | 22 |
+-----------+----------+-----------------------------+------------+
2. REPORT DETAILS
-----------------
TIMING-17#1 Warning
Non-clocked sequential cell
The clock pin FetchU/PC/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#2 Warning
Non-clocked sequential cell
The clock pin FetchU/PC/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#3 Warning
Non-clocked sequential cell
The clock pin FetchU/PC/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#4 Warning
Non-clocked sequential cell
The clock pin RF/r0/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#5 Warning
Non-clocked sequential cell
The clock pin RF/r0/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#6 Warning
Non-clocked sequential cell
The clock pin RF/r0/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#7 Warning
Non-clocked sequential cell
The clock pin RF/r0/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#8 Warning
Non-clocked sequential cell
The clock pin RF/r0/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#9 Warning
Non-clocked sequential cell
The clock pin RF/r0/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#10 Warning
Non-clocked sequential cell
The clock pin RF/r0/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#11 Warning
Non-clocked sequential cell
The clock pin RF/r0/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#12 Warning
Non-clocked sequential cell
The clock pin RF/r0/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#13 Warning
Non-clocked sequential cell
The clock pin RF/r1/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#14 Warning
Non-clocked sequential cell
The clock pin RF/r1/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#15 Warning
Non-clocked sequential cell
The clock pin RF/r1/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#16 Warning
Non-clocked sequential cell
The clock pin RF/r1/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#17 Warning
Non-clocked sequential cell
The clock pin RF/r1/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#18 Warning
Non-clocked sequential cell
The clock pin RF/r1/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#19 Warning
Non-clocked sequential cell
The clock pin RF/r1/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#20 Warning
Non-clocked sequential cell
The clock pin RF/r1/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#21 Warning
Non-clocked sequential cell
The clock pin RF/r1/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#22 Warning
Non-clocked sequential cell
The clock pin dM/memory_reg/CLKARDCLK is not reached by a timing clock
Related violations: <none>

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Mar 30 15:55:20 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Command : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
| Design : CPU9bits
| Device : xc7k160tifbg484-2L
| Design State : routed
| Grade : industrial
| Process : typical
| Characterization : Production
----------------------------------------------------------------------------------------------------------------------------------------------
Power Report
Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy
1. Summary
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 11.172 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 11.030 |
| Device Static (W) | 0.142 |
| Effective TJA (C/W) | 2.5 |
| Max Ambient (C) | 72.4 |
| Junction Temperature (C) | 52.6 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
| Design Nets Matched | NA |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
1.1 On-Chip Components
----------------------
+----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Slice Logic | 1.248 | 107 | --- | --- |
| LUT as Logic | 1.231 | 73 | 101400 | 0.07 |
| Register | 0.012 | 21 | 202800 | 0.01 |
| BUFG | 0.005 | 1 | 32 | 3.13 |
| Others | 0.000 | 4 | --- | --- |
| Signals | 1.328 | 114 | --- | --- |
| Block RAM | 0.060 | 0.5 | 325 | 0.15 |
| I/O | 8.393 | 12 | 285 | 4.21 |
| Static Power | 0.142 | | | |
| Total | 11.172 | | | |
+----------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
------------------------
+-----------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint | 0.950 | 2.849 | 2.775 | 0.074 |
| Vccaux | 1.800 | 0.707 | 0.687 | 0.020 |
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 3.975 | 3.974 | 0.001 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
| Vccbram | 0.950 | 0.007 | 0.005 | 0.002 |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 |
| Vccadc | 1.800 | 0.018 | 0.000 | 0.018 |
+-----------+-------------+-----------+-------------+------------+
1.3 Confidence Level
--------------------
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
2. Settings
-----------
2.1 Environment
---------------
+-----------------------+--------------------------+
| Ambient Temp (C) | 25.0 |
| ThetaJA (C/W) | 2.5 |
| Airflow (LFM) | 250 |
| Heat Sink | medium (Medium Profile) |
| ThetaSA (C/W) | 4.2 |
| Board Selection | medium (10"x10") |
| # of Board Layers | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0 |
+-----------------------+--------------------------+
2.2 Clock Constraints
---------------------
+-------+--------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------+--------+-----------------+
3. Detailed Reports
-------------------
3.1 By Hierarchy
----------------
+----------+-----------+
| Name | Power (W) |
+----------+-----------+
| CPU9bits | 11.030 |
| FetchU | 1.191 |
| PC | 1.191 |
| RF | 1.317 |
| r0 | 0.812 |
| r1 | 0.506 |
| dM | 0.113 |
+----------+-----------+

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Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 128 :
# of nets not needing routing.......... : 12 :
# of internally routed nets........ : 12 :
# of routable nets..................... : 116 :
# of fully routed nets............. : 116 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

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2012.4<EFBFBD>)Timing analysis from Implemented netlist.

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Mar 30 15:55:20 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Command : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation
| Design : CPU9bits
| Device : 7k160ti-fbg484
| Speed File : -2L PRODUCTION 1.12 2017-02-17
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : false
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
check_timing report
Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops
1. checking no_clock
--------------------
There are 22 register/latch pins with no clock driven by root clock pin: clk (HIGH)
2. checking constant_clock
--------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock
-----------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 75 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay
--------------------------
There is 1 input port with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay
---------------------------
There are 10 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock
--------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks
----------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops
-----------------
There are 0 combinational loops in the design.
10. checking partial_input_delay
--------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay
---------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops
------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
NA NA NA NA NA NA NA NA NA NA NA NA
There are no user specified timing constraints.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Mar 30 15:54:32 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
| Design : CPU9bits
| Device : 7k160tifbg484-2L
| Design State : Fully Placed
-------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs | 73 | 0 | 101400 | 0.07 |
| LUT as Logic | 73 | 0 | 101400 | 0.07 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 21 | 0 | 202800 | 0.01 |
| Register as Flip Flop | 21 | 0 | 202800 | 0.01 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+-------------------------+------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 21 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+--------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+--------------------------------------------+------+-------+-----------+-------+
| Slice | 21 | 0 | 25350 | 0.08 |
| SLICEL | 11 | 0 | | |
| SLICEM | 10 | 0 | | |
| LUT as Logic | 73 | 0 | 101400 | 0.07 |
| using O5 output only | 0 | | | |
| using O6 output only | 65 | | | |
| using O5 and O6 | 8 | | | |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| Slice Registers | 21 | 0 | 202800 | 0.01 |
| Register driven from within the Slice | 4 | | | |
| Register driven from outside the Slice | 17 | | | |
| LUT in front of the register is unused | 0 | | | |
| LUT in front of the register is used | 17 | | | |
| Unique Control Sets | 3 | | 25350 | 0.01 |
+--------------------------------------------+------+-------+-----------+-------+
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 0.5 | 0 | 325 | 0.15 |
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
| RAMB18 | 1 | 0 | 650 | 0.15 |
| RAMB18E1 only | 1 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 600 | 0.00 |
+-----------+------+-------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 12 | 0 | 285 | 4.21 |
| IOB Master Pads | 6 | | | |
| IOB Slave Pads | 5 | | | |
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
| PHASER_REF | 0 | 0 | 8 | 0.00 |
| OUT_FIFO | 0 | 0 | 32 | 0.00 |
| IN_FIFO | 0 | 0 | 32 | 0.00 |
| IDELAYCTRL | 0 | 0 | 8 | 0.00 |
| IBUFDS | 0 | 0 | 275 | 0.00 |
| GTXE2_COMMON | 0 | 0 | 1 | 0.00 |
| GTXE2_CHANNEL | 0 | 0 | 4 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 |
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
| ILOGIC | 0 | 0 | 285 | 0.00 |
| OLOGIC | 0 | 0 | 285 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
6. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 32 | 0.00 |
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
| BUFMRCE | 0 | 0 | 16 | 0.00 |
| BUFHCE | 0 | 0 | 120 | 0.00 |
| BUFR | 0 | 0 | 32 | 0.00 |
+------------+------+-------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| LUT6 | 37 | LUT |
| LUT4 | 27 | LUT |
| FDRE | 21 | Flop & Latch |
| OBUF | 10 | IO |
| LUT5 | 10 | LUT |
| LUT2 | 4 | LUT |
| LUT3 | 3 | LUT |
| IBUF | 2 | IO |
| RAMB18E1 | 1 | Block Memory |
| BUFG | 1 | Clock |
+----------+------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+

167
lab2CA.runs/impl_1/gen_run.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1553975561">
<File Type="BITSTR-BMM" Name="CPU9bits_bd.bmm"/>
<File Type="OPT-METHODOLOGY-DRC" Name="CPU9bits_methodology_drc_opted.rpt"/>
<File Type="INIT-TIMING" Name="CPU9bits_timing_summary_init.rpt"/>
<File Type="ROUTE-PWR" Name="CPU9bits_power_routed.rpt"/>
<File Type="PA-TCL" Name="CPU9bits.tcl"/>
<File Type="OPT-TIMING" Name="CPU9bits_timing_summary_opted.rpt"/>
<File Type="OPT-DCP" Name="CPU9bits_opt.dcp"/>
<File Type="ROUTE-PWR-SUM" Name="CPU9bits_power_summary_routed.pb"/>
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
<File Type="OPT-DRC" Name="CPU9bits_drc_opted.rpt"/>
<File Type="OPT-HWDEF" Name="CPU9bits.hwdef"/>
<File Type="PWROPT-DCP" Name="CPU9bits_pwropt.dcp"/>
<File Type="PWROPT-DRC" Name="CPU9bits_drc_pwropted.rpt"/>
<File Type="PWROPT-TIMING" Name="CPU9bits_timing_summary_pwropted.rpt"/>
<File Type="PLACE-DCP" Name="CPU9bits_placed.dcp"/>
<File Type="PLACE-IO" Name="CPU9bits_io_placed.rpt"/>
<File Type="PLACE-CLK" Name="CPU9bits_clock_utilization_placed.rpt"/>
<File Type="PLACE-UTIL" Name="CPU9bits_utilization_placed.rpt"/>
<File Type="PLACE-UTIL-PB" Name="CPU9bits_utilization_placed.pb"/>
<File Type="PLACE-CTRL" Name="CPU9bits_control_sets_placed.rpt"/>
<File Type="PLACE-SIMILARITY" Name="CPU9bits_incremental_reuse_placed.rpt"/>
<File Type="PLACE-PRE-SIMILARITY" Name="CPU9bits_incremental_reuse_pre_placed.rpt"/>
<File Type="BG-BGN" Name="CPU9bits.bgn"/>
<File Type="PLACE-TIMING" Name="CPU9bits_timing_summary_placed.rpt"/>
<File Type="POSTPLACE-PWROPT-DCP" Name="CPU9bits_postplace_pwropt.dcp"/>
<File Type="BG-BIN" Name="CPU9bits.bin"/>
<File Type="POSTPLACE-PWROPT-TIMING" Name="CPU9bits_timing_summary_postplace_pwropted.rpt"/>
<File Type="PHYSOPT-DCP" Name="CPU9bits_physopt.dcp"/>
<File Type="PHYSOPT-DRC" Name="CPU9bits_drc_physopted.rpt"/>
<File Type="BITSTR-MSK" Name="CPU9bits.msk"/>
<File Type="PHYSOPT-TIMING" Name="CPU9bits_timing_summary_physopted.rpt"/>
<File Type="ROUTE-ERROR-DCP" Name="CPU9bits_routed_error.dcp"/>
<File Type="ROUTE-DCP" Name="CPU9bits_routed.dcp"/>
<File Type="ROUTE-BLACKBOX-DCP" Name="CPU9bits_routed_bb.dcp"/>
<File Type="ROUTE-DRC" Name="CPU9bits_drc_routed.rpt"/>
<File Type="ROUTE-DRC-PB" Name="CPU9bits_drc_routed.pb"/>
<File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
<File Type="BITSTR-LTX" Name="CPU9bits.ltx"/>
<File Type="ROUTE-DRC-RPX" Name="CPU9bits_drc_routed.rpx"/>
<File Type="BITSTR-MMI" Name="CPU9bits.mmi"/>
<File Type="ROUTE-METHODOLOGY-DRC" Name="CPU9bits_methodology_drc_routed.rpt"/>
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="CPU9bits_methodology_drc_routed.rpx"/>
<File Type="BITSTR-SYSDEF" Name="CPU9bits.sysdef"/>
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="CPU9bits_methodology_drc_routed.pb"/>
<File Type="ROUTE-PWR-RPX" Name="CPU9bits_power_routed.rpx"/>
<File Type="ROUTE-STATUS" Name="CPU9bits_route_status.rpt"/>
<File Type="ROUTE-STATUS-PB" Name="CPU9bits_route_status.pb"/>
<File Type="ROUTE-TIMINGSUMMARY" Name="CPU9bits_timing_summary_routed.rpt"/>
<File Type="ROUTE-TIMING-PB" Name="CPU9bits_timing_summary_routed.pb"/>
<File Type="ROUTE-TIMING-RPX" Name="CPU9bits_timing_summary_routed.rpx"/>
<File Type="ROUTE-SIMILARITY" Name="CPU9bits_incremental_reuse_routed.rpt"/>
<File Type="ROUTE-CLK" Name="CPU9bits_clock_utilization_routed.rpt"/>
<File Type="ROUTE-BUS-SKEW" Name="CPU9bits_bus_skew_routed.rpt"/>
<File Type="ROUTE-BUS-SKEW-PB" Name="CPU9bits_bus_skew_routed.pb"/>
<File Type="ROUTE-BUS-SKEW-RPX" Name="CPU9bits_bus_skew_routed.rpx"/>
<File Type="POSTROUTE-PHYSOPT-DCP" Name="CPU9bits_postroute_physopt.dcp"/>
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="CPU9bits_postroute_physopt_bb.dcp"/>
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="CPU9bits_timing_summary_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="CPU9bits_timing_summary_postroute_physopted.pb"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="CPU9bits_timing_summary_postroute_physopted.rpx"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="CPU9bits_bus_skew_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="CPU9bits_bus_skew_postroute_physopted.pb"/>
<File Type="BG-BIT" Name="CPU9bits.bit"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="CPU9bits_bus_skew_postroute_physopted.rpx"/>
<File Type="BITSTR-RBT" Name="CPU9bits.rbt"/>
<File Type="BITSTR-NKY" Name="CPU9bits.nky"/>
<File Type="BG-DRC" Name="CPU9bits.drc"/>
<File Type="RDI-RDI" Name="CPU9bits.vdi"/>
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/ALU.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/ControlUnit.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/FetchUnit.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/dataMemory.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/instructionMemory.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/CPU9bits.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="CPU9bits"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</GenRun>

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lab2CA.runs/impl_1/htr.txt Normal file
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REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
REM
vivado -log CPU9bits.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace

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lab2CA.runs/impl_1/vivado.jou
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@@ -2,11 +2,11 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sun Mar 24 18:38:44 2019
# Process ID: 13064
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log CPU9bits_tb.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits_tb.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb.vdi
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou
# Start of session at: Sat Mar 30 15:53:31 2019
# Process ID: 13696
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits.vdi
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source CPU9bits_tb.tcl -notrace
source CPU9bits.tcl -notrace

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#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sun Mar 24 18:38:44 2019
# Process ID: 13064
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log CPU9bits_tb.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits_tb.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb.vdi
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source CPU9bits_tb.tcl -notrace

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1
lab2CA.runs/synth_1/CPU9bits_tb.tcl → lab2CA.runs/synth_1/CPU9bits.tcl
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@@ -17,7 +17,6 @@ proc create_report { reportName command } {
send_msg_id runtcl-5 warning "$msg"
}
}
set_param synth.incrementalSynthesisCache C:/Users/willi/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-18452-WM-G75VW/incrSyn
set_msg_config -id {Synth 8-256} -limit 10000
set_msg_config -id {Synth 8-638} -limit 10000
create_project -in_memory -part xc7k160tifbg484-2L

287
lab2CA.runs/synth_1/CPU9bits.vds
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@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sun Mar 24 16:57:48 2019
# Process ID: 9320
# Start of session at: Sat Mar 30 15:52:45 2019
# Process ID: 9028
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
@@ -15,115 +15,87 @@ Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 4932
WARNING: [Synth 8-1958] event expressions must result in a singular type [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:81]
INFO: Helper process launched with PID 18388
---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 376.207 ; gain = 113.672
Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 364.258 ; gain = 100.730
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
WARNING: [Synth 8-567] referenced signal 'writeEnable' should be on the sensitivity list [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:81]
WARNING: [Synth 8-567] referenced signal 'writeData' should be on the sensitivity list [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:81]
INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:266]
INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412]
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:766]
INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:766]
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:396]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:401]
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:396]
INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342]
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:325]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:331]
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:325]
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1300]
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1365]
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:676]
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:676]
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1365]
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1300]
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:713]
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:713]
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:632]
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:632]
INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541]
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
WARNING: [Synth 8-3848] Net result_O in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:842]
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:842]
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:916]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:916]
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:879]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:879]
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:309]
INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:309]
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1414]
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1414]
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:524]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:530]
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:524]
INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:17]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:13]
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996]
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996]
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356]
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:985]
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:985]
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:339]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:345]
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:339]
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (27#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0]
WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0]
WARNING: [Synth 8-3331] design shift_left has unconnected port A[8]
WARNING: [Synth 8-3331] design instructionMemory has unconnected port clk
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 414.008 ; gain = 151.473
Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 420.883 ; gain = 157.355
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 414.008 ; gain = 151.473
Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 420.883 ; gain = 157.355
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k160tifbg484-2L
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 420.883 ; gain = 157.355
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 414.008 ; gain = 151.473
---------------------------------------------------------------------------------
WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[15]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[14]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[13]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[12]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[11]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[10]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[9]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[8]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[7]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[6]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[5]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[4]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[3]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[2]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[1]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[0]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
WARNING: [Synth 8-327] inferring latch for variable 'dataMemEn_reg' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:26]
INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 461.227 ; gain = 198.691
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 420.883 ; gain = 157.355
---------------------------------------------------------------------------------
INFO: [Synth 8-223] decloning instance 'SE1' (sign_extend_3bit) to 'SE3'
@@ -140,18 +112,21 @@ Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 162
+---Registers :
9 Bit Registers := 9
9 Bit Registers := 10
+---RAMs :
4K Bit RAMs := 1
+---Muxes :
2 Input 9 Bit Muxes := 28
4 Input 9 Bit Muxes := 4
2 Input 4 Bit Muxes := 2
7 Input 9 Bit Muxes := 1
4 Input 9 Bit Muxes := 5
2 Input 9 Bit Muxes := 8
4 Input 4 Bit Muxes := 2
16 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 2
16 Input 3 Bit Muxes := 1
16 Input 2 Bit Muxes := 1
16 Input 1 Bit Muxes := 24
2 Input 1 Bit Muxes := 33
8 Input 2 Bit Muxes := 1
16 Input 1 Bit Muxes := 7
2 Input 1 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
@@ -159,16 +134,24 @@ Finished RTL Component Statistics
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module dataMemory
Module CPU9bits
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 20
16 Input 1 Bit Muxes := 16
2 Input 1 Bit Muxes := 32
4 Input 9 Bit Muxes := 1
8 Input 2 Bit Muxes := 1
Module instructionMemory
Detailed RTL Component Info :
+---Muxes :
7 Input 9 Bit Muxes := 1
Module dataMemory
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
+---RAMs :
4K Bit RAMs := 1
Module decoder
Detailed RTL Component Info :
+---Muxes :
2 Input 4 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
Module register
Detailed RTL Component Info :
@@ -193,7 +176,7 @@ Detailed RTL Component Info :
2 Input 3 Bit Muxes := 2
16 Input 3 Bit Muxes := 1
16 Input 2 Bit Muxes := 1
16 Input 1 Bit Muxes := 8
16 Input 1 Bit Muxes := 7
Module bit1_mux_2_1
Detailed RTL Component Info :
+---Muxes :
@@ -216,23 +199,24 @@ Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 723.004 ; gain = 460.469
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 598.238 ; gain = 334.711
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
ROM:
+------------------+------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------------+------------+---------------+----------------+
|instructionMemory | p_0_out | 64x9 | LUT |
|CPU9bits | p_0_out | 64x9 | LUT |
+------------------+------------+---------------+----------------+
Block RAM: Preliminary Mapping Report (see note below)
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|dataMemory: | memory_reg | 512 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
INFO: [Synth 8-6837] The timing for the instance i_1/dM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
Report RTL Partitions:
+-+--------------+------------+----------+
@@ -244,7 +228,21 @@ No constraint files found.
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 723.004 ; gain = 460.469
Finished Timing Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 598.238 ; gain = 334.711
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Block RAM: Final Mapping Report
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|dataMemory: | memory_reg | 512 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -255,8 +253,9 @@ Report RTL Partitions:
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-6837] The timing for the instance dM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 723.004 ; gain = 460.469
Finished Technology Mapping : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 598.238 ; gain = 334.711
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -280,7 +279,7 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
---------------------------------------------------------------------------------
Report Check Netlist:
@@ -293,7 +292,7 @@ Report Check Netlist:
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -305,25 +304,25 @@ Report RTL Partitions:
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -336,65 +335,55 @@ Report BlackBoxes:
+-+--------------+----------+
Report Cell Usage:
+------+------+------+
| |Cell |Count |
+------+------+------+
|1 |BUFG | 2|
|2 |LUT2 | 45|
|3 |LUT3 | 50|
|4 |LUT4 | 51|
|5 |LUT5 | 69|
|6 |LUT6 | 439|
|7 |MUXF7 | 6|
|8 |FDRE | 81|
|9 |LD | 154|
|10 |IBUF | 2|
|11 |OBUF | 1|
+------+------+------+
+------+---------+------+
| |Cell |Count |
+------+---------+------+
|1 |BUFG | 1|
|2 |LUT2 | 4|
|3 |LUT3 | 3|
|4 |LUT4 | 27|
|5 |LUT5 | 10|
|6 |LUT6 | 37|
|7 |RAMB18E1 | 1|
|8 |FDRE | 21|
|9 |IBUF | 2|
|10 |OBUF | 10|
+------+---------+------+
Report Instance Areas:
+------+---------+------------+------+
| |Instance |Module |Cells |
+------+---------+------------+------+
|1 |top | | 900|
|2 | Bank |RegFile | 45|
|3 | r0 |register_5 | 16|
|4 | r1 |register_6 | 9|
|5 | r2 |register_7 | 10|
|6 | r3 |register_8 | 10|
|7 | CU |ControlUnit | 14|
|8 | FetchU |FetchUnit | 126|
|9 | PC |register_4 | 126|
|10 | RF |RegFile_0 | 345|
|11 | r0 |register | 216|
|12 | r1 |register_1 | 14|
|13 | r2 |register_2 | 100|
|14 | r3 |register_3 | 15|
|15 | dM |dataMemory | 365|
+------+---------+------------+------+
+------+---------+-----------+------+
| |Instance |Module |Cells |
+------+---------+-----------+------+
|1 |top | | 116|
|2 | FetchU |FetchUnit | 31|
|3 | PC |register_1 | 31|
|4 | RF |RegFile | 71|
|5 | r0 |register | 42|
|6 | r1 |register_0 | 29|
|7 | dM |dataMemory | 1|
+------+---------+-----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 29 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
Synthesis Optimization Complete : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 160 Unisim elements for replacement
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 723.004 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 684.082 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 154 instances were transformed.
LD => LDCE: 154 instances
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
70 Infos, 29 Warnings, 0 Critical Warnings and 0 Errors encountered.
73 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 723.004 ; gain = 473.363
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 723.004 ; gain = 0.000
synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 684.082 ; gain = 433.695
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 684.082 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sun Mar 24 16:58:31 2019...
INFO: [Common 17-206] Exiting Vivado at Sat Mar 30 15:53:22 2019...

BIN
lab2CA.runs/synth_1/CPU9bits_tb.dcp
View File

Binary file not shown.

951
lab2CA.runs/synth_1/CPU9bits_tb.vds
View File

@@ -1,951 +0,0 @@
#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sun Mar 24 18:28:31 2019
# Process ID: 5228
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log CPU9bits_tb.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.vds
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source CPU9bits_tb.tcl -notrace
Command: synth_design -top CPU9bits_tb -part xc7k160tifbg484-2L
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 14244
WARNING: [Synth 8-1958] event expressions must result in a singular type [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:85]
---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 372.199 ; gain = 114.445
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'CPU9bits_tb' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:172]
WARNING: [Synth 8-85] always block has no event control specified [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:179]
INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
WARNING: [Synth 8-567] referenced signal 'writeEnable' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:85]
WARNING: [Synth 8-567] referenced signal 'writeData' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:85]
INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412]
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342]
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541]
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
WARNING: [Synth 8-3848] Net result_O in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:17]
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996]
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996]
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356]
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (27#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits_tb' (28#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:172]
WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0]
WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0]
WARNING: [Synth 8-3331] design shift_left has unconnected port A[8]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:01:51 ; elapsed = 00:01:54 . Memory (MB): peak = 2338.125 ; gain = 2080.371
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:02:04 ; elapsed = 00:02:09 . Memory (MB): peak = 2338.125 ; gain = 2080.371
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k160tifbg484-2L
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:02:04 ; elapsed = 00:02:09 . Memory (MB): peak = 2338.125 ; gain = 2080.371
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "memory_reg[511]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[510]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[509]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[508]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[507]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[506]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[505]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[504]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[503]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[502]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[501]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[500]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[499]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[498]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[497]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[496]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[495]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[494]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[493]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[492]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[491]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[490]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[489]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[488]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[487]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[486]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[485]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[484]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[483]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[482]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[481]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[480]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[479]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[478]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[477]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[476]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[475]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[474]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[473]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[472]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[471]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[470]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[469]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[468]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[467]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[466]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[465]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[464]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[463]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[462]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[461]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[460]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[459]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[458]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[457]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[456]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[455]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[454]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[453]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[452]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[451]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[450]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[449]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[448]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[447]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[446]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[445]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[444]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[443]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[442]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[441]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[440]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[439]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[438]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[437]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[436]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[435]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[434]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[433]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[432]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[431]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[430]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[429]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[428]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[427]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[426]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[425]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[424]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[423]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[422]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[421]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[420]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[419]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[418]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[417]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[416]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[415]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[414]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[413]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[412]" won't be mapped to RAM because it is too sparse
INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:202]
WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[511]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[510]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[509]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[508]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[507]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[506]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[505]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[504]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[503]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[502]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[501]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[500]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[499]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[498]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[497]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[496]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[495]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[494]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[493]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[492]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[491]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[490]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[489]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[488]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[487]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[486]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[485]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[484]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[483]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[482]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[481]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[480]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[479]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[478]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[477]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[476]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[475]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[474]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[473]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[472]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[471]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[470]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[469]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[468]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[467]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[466]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[465]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[464]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[463]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[462]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[461]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[460]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[459]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[458]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[457]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[456]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[455]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[454]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[453]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[452]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[451]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[450]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[449]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[448]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[447]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[446]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[445]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[444]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[443]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[442]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[441]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[440]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[439]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[438]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[437]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[436]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[435]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[434]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[433]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[432]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[431]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[430]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[429]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[428]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[427]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[426]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[425]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[424]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[423]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[422]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[421]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[420]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[419]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[418]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[417]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[416]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[415]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[414]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
INFO: [Common 17-14] Message 'Synth 8-327' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:04:25 ; elapsed = 00:04:33 . Memory (MB): peak = 2906.012 ; gain = 2648.258
---------------------------------------------------------------------------------
INFO: [Synth 8-223] decloning instance 'CPU9bits0/SE1' (sign_extend_3bit) to 'CPU9bits0/SE3'
Report RTL Partitions:
+------+----------------+------------+----------+
| |RTL Partition |Replication |Instances |
+------+----------------+------------+----------+
|1 |dataMemory__GB0 | 1| 2378380|
|2 |CPU9bits__GC0 | 1| 1169|
+------+----------------+------------+----------+
No constraint files found.
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 162
+---Registers :
9 Bit Registers := 9
+---Muxes :
2 Input 9 Bit Muxes := 520
8 Input 9 Bit Muxes := 1
4 Input 9 Bit Muxes := 4
2 Input 4 Bit Muxes := 2
4 Input 4 Bit Muxes := 2
16 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 2
16 Input 3 Bit Muxes := 1
16 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 513
16 Input 1 Bit Muxes := 8
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module dataMemory
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 512
2 Input 1 Bit Muxes := 512
Module instructionMemory
Detailed RTL Component Info :
+---Muxes :
8 Input 9 Bit Muxes := 1
Module decoder__1
Detailed RTL Component Info :
+---Muxes :
2 Input 4 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
Module register__8
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module register__7
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module register__6
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module register__5
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module mux_4_1__3
Detailed RTL Component Info :
+---Muxes :
4 Input 9 Bit Muxes := 1
Module mux_4_1__2
Detailed RTL Component Info :
+---Muxes :
4 Input 9 Bit Muxes := 1
Module decoder
Detailed RTL Component Info :
+---Muxes :
2 Input 4 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
Module register__2
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module register__3
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module register__4
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module register
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module mux_4_1__1
Detailed RTL Component Info :
+---Muxes :
4 Input 9 Bit Muxes := 1
Module mux_4_1
Detailed RTL Component Info :
+---Muxes :
4 Input 9 Bit Muxes := 1
Module register__1
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module add_1bit__44
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__43
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__42
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__41
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__40
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__39
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__38
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__37
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__36
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module mux_2_1__1
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 1
Module add_1bit__35
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__34
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__33
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__32
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__31
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__30
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__29
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__28
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__27
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__62
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__61
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__60
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__59
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__58
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__57
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__56
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__55
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__54
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__26
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__25
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__24
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__23
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__22
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__21
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__20
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__19
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__18
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__80
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__79
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__78
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__77
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__76
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__75
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__74
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__73
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__72
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__71
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__70
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__69
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__68
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__67
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__66
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__65
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__64
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__63
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module ControlUnit
Detailed RTL Component Info :
+---Muxes :
16 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 2
16 Input 3 Bit Muxes := 1
16 Input 2 Bit Muxes := 1
16 Input 1 Bit Muxes := 8
Module add_1bit__53
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__52
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__51
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__50
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__49
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__48
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__47
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__46
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__45
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module mux_2_1__2
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 1
Module add_1bit__17
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__16
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__15
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__14
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__13
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__12
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__11
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__10
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__9
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module mux_2_1__3
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 1
Module mux_2_1__4
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 1
Module bit1_mux_2_1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module add_1bit__1
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__2
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__3
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__4
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__5
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__6
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__7
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__8
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module mux_2_1__5
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 1
Module mux_2_1__6
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 1
Module mux_2_1__7
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 1
Module mux_2_1
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 600 (col length:100)
BRAMs: 650 (col length: RAMB18 100 RAMB36 50)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
No constraint files found.
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
INFO: [Synth 8-3886] merging instance 'CPU9bits0i_1/iM/readData_reg[0]' (LD) to 'CPU9bits0i_1/iM/readData_reg[2]'
INFO: [Synth 8-3886] merging instance 'CPU9bits0i_1/iM/readData_reg[8]' (LD) to 'CPU9bits0i_1/iM/readData_reg[6]'
INFO: [Synth 8-3886] merging instance 'CPU9bits0i_1/iM/readData_reg[2]' (LD) to 'CPU9bits0i_1/iM/readData_reg[4]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\iM/readData_reg[4] )
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:09:23 ; elapsed = 00:09:37 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
No constraint files found.
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:09:23 ; elapsed = 00:09:37 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:09:23 ; elapsed = 00:09:37 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+-+-----+------+
| |Cell |Count |
+-+-----+------+
+-+-----+------+
Report Instance Areas:
+------+---------+-------+------+
| |Instance |Module |Cells |
+------+---------+-------+------+
|1 |top | | 0|
+------+---------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 526 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
Synthesis Optimization Complete : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3340.348 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
177 Infos, 111 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:09:36 ; elapsed = 00:10:01 . Memory (MB): peak = 3340.348 ; gain = 3090.086
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 3340.348 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_tb_utilization_synth.rpt -pb CPU9bits_tb_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sun Mar 24 18:38:37 2019...

BIN
lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.pb
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BIN
lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
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56
lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt → lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sun Mar 24 16:58:30 2019
| Date : Sat Mar 30 15:53:22 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
| Design : CPU9bits
@@ -30,13 +30,13 @@ Table of Contents
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 578 | 0 | 101400 | 0.57 |
| LUT as Logic | 578 | 0 | 101400 | 0.57 |
| Slice LUTs* | 73 | 0 | 101400 | 0.07 |
| LUT as Logic | 73 | 0 | 101400 | 0.07 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 235 | 0 | 202800 | 0.12 |
| Register as Flip Flop | 81 | 0 | 202800 | 0.04 |
| Register as Latch | 154 | 0 | 202800 | 0.08 |
| F7 Muxes | 6 | 0 | 50700 | 0.01 |
| Slice Registers | 21 | 0 | 202800 | 0.01 |
| Register as Flip Flop | 21 | 0 | 202800 | 0.01 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+-------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
@@ -55,22 +55,23 @@ Table of Contents
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 154 | Yes | - | Reset |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 81 | Yes | Reset | - |
| 21 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 325 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
| RAMB18 | 0 | 0 | 650 | 0.00 |
+----------------+------+-------+-----------+-------+
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 0.5 | 0 | 325 | 0.15 |
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
| RAMB18 | 1 | 0 | 650 | 0.15 |
| RAMB18E1 only | 1 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
@@ -90,7 +91,7 @@ Table of Contents
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 3 | 0 | 285 | 1.05 |
| Bonded IOB | 12 | 0 | 285 | 4.21 |
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
@@ -117,7 +118,7 @@ Table of Contents
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 2 | 0 | 32 | 6.25 |
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 32 | 0.00 |
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
@@ -151,17 +152,16 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| LUT6 | 439 | LUT |
| LDCE | 154 | Flop & Latch |
| FDRE | 81 | Flop & Latch |
| LUT5 | 69 | LUT |
| LUT4 | 51 | LUT |
| LUT3 | 50 | LUT |
| LUT2 | 45 | LUT |
| MUXF7 | 6 | MuxFx |
| LUT6 | 37 | LUT |
| LUT4 | 27 | LUT |
| FDRE | 21 | Flop & Latch |
| OBUF | 10 | IO |
| LUT5 | 10 | LUT |
| LUT2 | 4 | LUT |
| LUT3 | 3 | LUT |
| IBUF | 2 | IO |
| BUFG | 2 | Clock |
| OBUF | 1 | IO |
| RAMB18E1 | 1 | Block Memory |
| BUFG | 1 | Clock |
+----------+------+---------------------+

5
lab2CA.runs/synth_1/gen_run.xml
View File

@@ -1,9 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1553461063">
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1553975560">
<File Type="PA-TCL" Name="CPU9bits.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="CPU9bits_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
<File Type="RDS-RDS" Name="CPU9bits.vds"/>
<File Type="RDS-DCP" Name="CPU9bits.dcp"/>
<File Type="VDS-TIMINGSUMMARY" Name="CPU9bits_timing_summary_synth.rpt"/>
<File Type="VDS-TIMING-PB" Name="CPU9bits_timing_summary_synth.pb"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/ALU.v">

2
lab2CA.runs/synth_1/htr.txt
View File

@@ -6,4 +6,4 @@ REM to be invoked for Vivado to track run status.
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
REM
vivado -log CPU9bits_tb.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl
vivado -log CPU9bits.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl

4
lab2CA.runs/synth_1/vivado.jou
View File

@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sun Mar 24 16:57:48 2019
# Process ID: 9320
# Start of session at: Sat Mar 30 15:52:45 2019
# Process ID: 9028
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds

BIN
lab2CA.runs/synth_1/vivado.pb
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2
lab2CA.sim/sim_1/behav/xsim/dataMemory_tb.tcl
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@@ -8,4 +8,4 @@ if { [string length $curr_wave] == 0 } {
}
}
run 1000ns
run 100000ns

6
lab2CA.sim/sim_1/behav/xsim/webtalk.jou
View File

@@ -2,10 +2,10 @@
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sun Mar 24 17:05:08 2019
# Process ID: 16036
# Start of session at: Fri Mar 29 15:28:37 2019
# Process ID: 28052
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------

12
lab2CA.sim/sim_1/behav/xsim/webtalk_13536.backup.jou
View File

@@ -1,12 +0,0 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sun Mar 24 17:24:25 2019
# Process ID: 13536
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace

4
lab2CA.sim/sim_1/behav/xsim/webtalk_14824.backup.jou → lab2CA.sim/sim_1/behav/xsim/webtalk_14652.backup.jou
View File

@@ -2,8 +2,8 @@
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sun Mar 24 16:59:36 2019
# Process ID: 14824
# Start of session at: Fri Mar 29 15:13:54 2019
# Process ID: 14652
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log

12
lab2CA.sim/sim_1/behav/xsim/webtalk_26660.backup.jou Normal file
View File

@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Fri Mar 29 15:21:59 2019
# Process ID: 26660
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/REPOSITORIES/Educational/Western -notrace

4
lab2CA.sim/sim_1/behav/xsim/webtalk_42696.backup.jou → lab2CA.sim/sim_1/behav/xsim/webtalk_5080.backup.jou
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@@ -2,8 +2,8 @@
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Fri Mar 22 17:35:57 2019
# Process ID: 42696
# Start of session at: Fri Mar 29 15:24:02 2019
# Process ID: 5080
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log

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lab2CA.sim/sim_1/behav/xsim/xelab.pb
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32
lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
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@@ -1,32 +0,0 @@
webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Sun Mar 24 19:55:57 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device"
webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device"
webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device"
webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "138" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment"
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "50015 ns" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.25_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "7896_KB" -context "xsim\\usage"
webtalk_transmit -clientid 2553943341 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

BIN
lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
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17
lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/obj/xsim_1.c
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@@ -45,30 +45,29 @@
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
extern void execute_2(char*, char *);
extern void execute_3(char*, char *);
extern void execute_7(char*, char *);
extern void execute_6(char*, char *);
extern void execute_11(char*, char *);
extern void execute_12(char*, char *);
extern void execute_13(char*, char *);
extern void execute_14(char*, char *);
extern void execute_15(char*, char *);
extern void execute_16(char*, char *);
extern void execute_4(char*, char *);
extern void execute_5(char*, char *);
extern void execute_6(char*, char *);
extern void execute_8(char*, char *);
extern void execute_9(char*, char *);
extern void execute_10(char*, char *);
extern void execute_11(char*, char *);
extern void execute_16(char*, char *);
extern void execute_17(char*, char *);
extern void execute_18(char*, char *);
extern void execute_19(char*, char *);
extern void execute_20(char*, char *);
extern void execute_21(char*, char *);
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[19] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_7, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_5, (funcp)execute_6, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)vlog_transfunc_eventcallback};
const int NumRelocateId= 19;
funcp funcTab[18] = {(funcp)execute_2, (funcp)execute_6, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_4, (funcp)execute_5, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)vlog_transfunc_eventcallback};
const int NumRelocateId= 18;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/dataMemory_tb_behav/xsim.reloc", (void **)funcTab, 19);
iki_relocate(dp, "xsim.dir/dataMemory_tb_behav/xsim.reloc", (void **)funcTab, 18);
/*Populate the transaction function pointer field in the whole net structure */
}

22
lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl
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@@ -1,10 +1,10 @@
webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/
webtalk_init -webtalk_dir C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Sun Mar 24 17:39:03 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key date_generated -value "Fri Mar 29 15:35:47 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device"
webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device"
webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device"
webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device"
webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device"
@@ -12,21 +12,21 @@ webtalk_add_data -client project -key target_family -value "not_applicable" -con
webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "f67bb5263bf851bf9c1beaa84fe1017c" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "22" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "5" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "2395 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "17.000 GB" -context "user_environment"
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "60 ns" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.05_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "6128_KB" -context "xsim\\usage"
webtalk_transmit -clientid 918939418 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_add_data -client xsim -key Simulation_Time -value "0.08_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "5520_KB" -context "xsim\\usage"
webtalk_transmit -clientid 3479297430 -regid "" -xml C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

BIN
lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/xsim.mem
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BIN
lab2CA.sim/sim_1/behav/xsim/xvlog.pb
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20
lab2CA.srcs/sources_1/new/ALU.v
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@@ -10,8 +10,8 @@ module ALU(
// Wires for connecting the modules to the mux
wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H,result_I,result_J,result_K,result_L,result_M,result_N,result_O,result_P;
wire cout;
// A (0000) - Add
// A (0000) - Add
add_9bit add0(
.A(operand0),
.B(operand1),
@@ -41,15 +41,15 @@ module ALU(
.C(result_E));
// F (0101) - Shift Left
shift_left sl(
.A(operand0),
.A(operand0[7:0]),
.B(result_F));
// G (0110) - Shift Right Logical
shift_right_logical srl(
.A(operand0),
.A(operand0[8:1]),
.B(result_G));
// H (0111) - Shift Right Arithmetic
shift_right_arithmetic sra(
.A(operand0),
.A(operand0[8:1]),
.B(result_H));
// I (1000) - NOT
not_9bit not0(
@@ -65,8 +65,6 @@ module ALU(
.A(operand0),
.B(result_K));
// L (1011)
// Will hacked in here
// M (1100)
// N (1101)
// O (1110)
@@ -87,10 +85,10 @@ module ALU(
.J(result_J),
.K(result_K),
.L(9'b000000000),
.M(result_M),
.N(result_N),
.O(result_O),
.P(result_P),
.M(9'b111111111), // Currently not used
.N(9'b111111111), // Currently not used
.O(9'b111111111), // Currently not used
.P(9'b111111111), // Currently not used
.out(result));

55
lab2CA.srcs/sources_1/new/BasicModules.v
View File

@@ -259,43 +259,32 @@ module comparator_tb();
endmodule
module decoder (
input wire en,
input wire [1:0] index,
output reg [3:0] regOut);
always @(en, index)begin
if(en == 0)begin
case(index)
2'b00: regOut <= 4'b1110;
2'b01: regOut <= 4'b1101;
2'b10: regOut <= 4'b1011;
2'b11: regOut <= 4'b0111;
default: regOut <= 4'b1111;
endcase
end
else begin
regOut <= 4'b1111;
end
end
always @ (index)
case(index)
2'b00: regOut <= 4'b1110;
2'b01: regOut <= 4'b1101;
2'b10: regOut <= 4'b1011;
2'b11: regOut <= 4'b0111;
default: regOut <= 4'b1111;
endcase
endmodule
//testbench
module decoder_tb();
reg enable;
reg [1:0] indexIn;
wire [3:0] regOut;
decoder dec0(
.en(enable),
.index(indexIn),
.regOut(regOut));
.regOut(regOut)
);
initial begin
enable = 0;
indexIn = 2'b00;
#5
enable = 1;
#5
indexIn = 2'b01;
#5
indexIn = 2'b10;
@@ -885,7 +874,7 @@ module eMPipReg(
endmodule
module shift_left(
input wire [8:0] A,
input wire [7:0] A,
output wire [8:0] B);
assign B = {A[7:0],1'b0};
@@ -921,20 +910,20 @@ module shift_left_tb();
end
endmodule
module shift_right_logical(
input wire [8:0] A,
module shift_right_arithmetic(
input wire [8:1] A,
output wire [8:0] B);
assign B = {1'b0,A[8:1]};
assign B = {A[8],A[8:1]};
endmodule
//testbench
module shift_right_logical_tb();
module shift_right_arithmetic_tb();
reg [8:0] a;
wire [8:0] b;
shift_right_logical tb0(
shift_right_arithmetic tb0(
.A(a),
.B(b));
@@ -958,21 +947,21 @@ module shift_right_logical_tb();
end
endmodule
module shift_right_arithmetic(
input wire [8:0] A,
module shift_right_logical(
input wire [8:1] A,
output wire [8:0] B);
assign B = {A[8],A[8:1]};
assign B = {1'b0,A[8:1]};
endmodule
//testbench
module shift_right_arithmetic_tb();
module shift_right_logical_tb();
reg [8:0] a;
wire [8:0] b;
shift_right_arithmetic tb0(
shift_right_logical tb0(
.A(a),
.B(b));

153
lab2CA.srcs/sources_1/new/CPU9bits.v
View File

@@ -2,33 +2,32 @@
module CPU9bits(
input wire reset, clk,
output reg [8:0] result,
output wire done
);
wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N, bankData, bankOP,jumpNeg;
wire [2:0] FU;
wire [3:0] aluOp;
wire [2:0] FU;
wire [1:0] bankS;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link, js, dataMemEn;
instructionMemory iM(
.clk(clk),
.address(PCout),
.readData(instr)
);
);
dataMemory dM(
.clk(clk),
.writeEnable(dataMemEn),
.writeData(op0),
.address(op1),
.readData(dataMemOut)
);
);
RegFile RF(
.clk(clk),
.reset(reset),
.enable(RegEn),
.write_index(instr[4:3]),
.op0_idx(instr[4:3]),
.op1_idx(instr[2:1]),
@@ -36,11 +35,10 @@ module CPU9bits(
.op0(op0),
.op1(op1)
);
RegFile Bank(
.clk(clk),
.reset(reset),
.enable(bankS[1]),
.write_index(instr[2:1]),
.op0_idx(instr[2:1]),
.op1_idx(2'b00),//Doesn't matter
@@ -48,23 +46,23 @@ module CPU9bits(
.op0(bankOP),
.op1()
);
FetchUnit FetchU(
.clk(clk),
.reset(reset),
.op_idx(fetchBranch),
.AddrIn(FUAddr),
.AddrOut(PCout)
);
ALU alu(
);
ALU alu(
.opcode(aluOp),
.operand0(op0),
.operand1(op1),
.result(AluOut)
);
ControlUnit CU(
);
ControlUnit CU(
.instIn(instr[8:5]),
.functBit(instr[0]),
.aluOut(aluOp),
@@ -77,108 +75,136 @@ module CPU9bits(
.link(link),
.bank(bankS),
.js(js)
);
);
//-----------------------Fetch Unit Stuff
add_9bit JBAdder(
add_9bit JBAdder(
.A(PCout),
.B(JBRes),
.Cin(1'b0),
.Sum(FUJB),
.Cout(cout0));
.Cout(cout0)
);
mux_2_1 mux0(
.A(op0),
.B(FUJB),
.out(FUAddr),
.switch(FU[1]));
twos_compliment_9bit two_comp0(
.switch(FU[1])
);
twos_compliment_9bit two_comp0(
.A({4'b0000,instr[4:0]}),
.B(jumpNeg));
.B(jumpNeg)
);
mux_2_1 mux1(
.A({4'b0000,instr[4:0]}),
.B(jumpNeg),
.out(SE2N),
.switch(js));
.switch(js)
);
mux_2_1 mux2(
.A(SE2N), //Jump -- Change with signer module!
.B(SE1N),//Branch -- Change with signer module!
.out(JBRes),
.switch(FU[2]));
.switch(FU[2])
);
sign_extend_3bit SE1(
.A(instr[2:0]),
.B(SE1N));
.B(SE1N)
);
bit1_mux_2_1 BranMux( // BEQ MUX
.A(FU[0]),
.B(AluOut[0]),
.out(fetchBranch),
.switch(FU[2])); // FU[2] only goes high when BEQ
.switch(FU[2]) // FU[2] only goes high when BEQ
);
///--------------------------Addi Stuff
add_9bit Addier(
.A(SE3N), // Change with signer module!
.B(op0),
.Cin(1'b0),
.Sum(AddiOut),
.Cout(cout1));
.Cout(cout1)
);
sign_extend_3bit SE3(
.A(instr[2:0]),
.B(SE3N));
.B(SE3N)
);
mux_2_1 mux3(
.A(AluOut),
.B(AddiOut),
.out(loadMux),
.switch(addiS));
.switch(addiS)
);
///--------------------------Mem stuff
mux_2_1 mux4(
.A(linkData),
.B(dataMemOut), // This is DATA MEM
.out(bankData),
.switch(loadS));
.switch(loadS)
);
///--------------------------Bank stuff
mux_2_1 mux5(
.A(bankData),
.B(bankOP),
.out(RFIn),
.switch(bankS[0]));
.switch(bankS[0])
);
///--------------------------Link Stuff
mux_2_1 mux6(
.A(loadMux),
.B(PCout),
.out(linkData),
.switch(link));
.switch(link)
);
always @ (instr, dataMemOut, AluOut, AddiOut)
begin
case(instr[8:5])
4'b0001: // Load Byte
result <= dataMemOut;
4'b0101: // Add/Subtract
result <= AluOut;
4'b0110: // Add Immediate
result <= AddiOut;
4'b0111: // Set if Less Than
result <= AluOut;
4'b1101: // NOR
result <= AluOut;
4'b1110: // OR/AND
result <= AluOut;
4'b1111: // Shift Right Logical/Shift Left Logical
result <= AluOut;
default:
result <= 9'bXXXXXXXXX;
endcase
end
endmodule
module CPU9bits_tb();
reg clk, reset;
wire done;
initial begin
clk = 1'b0;
end
always begin
always
#5 clk = ~clk; // Period to be determined
end
CPU9bits CPU9bits0(
.reset(reset),
@@ -186,6 +212,7 @@ module CPU9bits_tb();
.done(done));
initial begin
clk = 1'b0;
#5
reset = 1'b1;
#10

524
lab2CA.srcs/sources_1/new/ControlUnit.v
View File

@@ -5,270 +5,286 @@ module ControlUnit(
input wire functBit,
output reg [3:0] aluOut,
output reg [2:0] FU,
output reg addi,
output reg mem, dataMemEn,
output reg RegEn,
output reg halt,
output reg link,
output reg [1:0] bank,
output reg js);
output reg addi, mem, dataMemEn, RegEn, halt, link, js);
always @(instIn, functBit)begin
case(instIn)
4'b0101:
if(functBit == 1) begin
aluOut <= 4'b0001; //sub
RegEn <= 1'b0;
FU <= 3'b001;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
else begin
aluOut <= 4'b0000; //Add
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1101: begin
aluOut <= 4'b0011; //nor
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0100: begin
aluOut <= 4'b1011; //zero
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1110:
if(functBit == 1) begin
aluOut <= 4'b0100; //and
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
else begin
aluOut <= 4'b0010; //or
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1111:
if(functBit == 1) begin
aluOut <= 4'b0110; //srl
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
else begin
aluOut <= 4'b0101; //shift left
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0111: begin
aluOut <= 4'b1001; //Less than
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0110: begin
aluOut <= 4'b1010;
addi <= 1'b1; // addi
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1001: begin
aluOut <= 4'b0000;
FU <= 3'b010; // jf
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1011: begin
aluOut <= 4'b0000;
FU <= 3'b010; // jb
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b1;
end
4'b0011: begin // link
halt <= 1'b0;
RegEn <= 1'b0;
FU <= 3'b001;
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b1;
bank <= 2'b10;
js <= 1'b0;
end
4'b1100: begin
aluOut <= 4'b1010;
FU <= 3'b110; // branch
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1000: begin
aluOut <= 4'b0000;
FU <= 3'b000; // jumpreg
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0001: begin
aluOut <= 4'b0000;
mem <= 1'b1; // load
dataMemEn <= 1'b0;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
halt <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0010: begin
aluOut <= 4'b0000;
mem <= 1'b0; // store
dataMemEn <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1010: begin
halt <= 1'b0; // bank
RegEn <= !functBit;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= {functBit,functBit};
js <= 1'b0;
end
4'b0000: begin
halt <= 1'b1; // halt
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
default: begin
halt <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001;
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
always @(instIn, functBit)
begin
case(instIn)
4'b0000: // Halt/NOP
begin
halt <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0001: // Load Byte
begin
aluOut <= 4'b0000;
mem <= 1'b1;
dataMemEn <= 1'b0; // Disabled
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
halt <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0010: // Store Byte
begin
aluOut <= 4'b0000;
mem <= 1'b0;
dataMemEn <= 1'b1; // Enabled
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0011: // Link
begin
halt <= 1'b0;
RegEn <= 1'b0;
FU <= 3'b001;
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b1;
bank <= 2'b10;
js <= 1'b0;
end
4'b0100: // Zero
begin
aluOut <= 4'b1011;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0101: // Add/Subtract
if(functBit == 1) begin // Subtract
aluOut <= 4'b0001;
RegEn <= 1'b0;
FU <= 3'b001;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
else begin // Add
aluOut <= 4'b0000;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0110: // Add Immediate
begin
aluOut <= 4'b1010;
addi <= 1'b1;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0111: // Set if Less Than
begin
aluOut <= 4'b1001;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1000: // Jump to Register
begin
aluOut <= 4'b0000;
FU <= 3'b000;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1001: // Jump Forward
begin
aluOut <= 4'b0000;
FU <= 3'b010;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1010: // Bank Load/Bank Store
begin
halt <= 1'b0;
RegEn <= !functBit;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
aluOut <= 4'b0000;
dataMemEn <= 1'b0; // Disabled
mem <= 1'b0;
link <= 1'b0;
bank <= {functBit,functBit};
js <= 1'b0;
end
4'b1011: // Jump Backward
begin
aluOut <= 4'b0000;
FU <= 3'b010;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b1;
end
4'b1100: // Branch if Zero
begin
aluOut <= 4'b1010;
FU <= 3'b110;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1101: // NOR
begin
aluOut <= 4'b0011;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1110: // OR/AND
if(functBit == 1) // AND
begin
aluOut <= 4'b0100;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
else // OR
begin
aluOut <= 4'b0010;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1111: // Shift Right Logical/Shift Left Logical
if(functBit == 1) // Shift Right Logical
begin
aluOut <= 4'b0110;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
else // Shift Left Logical
begin
aluOut <= 4'b0101;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
default:
begin
halt <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001;
dataMemEn <= 1'b0; // Disabled
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
endcase
end
endmodule
module ControlUnit_tb();
reg [3:0] instruction;
reg functionB;
wire [3:0] aluOutput;
wire [2:0] FetchUnit;
wire addImmediate;
wire memory;
wire RegEnable;
wire addImmediate, memory, RegEnable;
ControlUnit ControlUnit0(
.instIn(instruction),

7
lab2CA.srcs/sources_1/new/RegFile.v
View File

@@ -1,6 +1,6 @@
`timescale 1ns / 1ps
module RegFile(input wire clk, reset, enable,
module RegFile(input wire clk, reset,
input wire [1:0] write_index, op0_idx, op1_idx,
input wire [8:0] write_data,
output wire [8:0] op0, op1);
@@ -11,7 +11,6 @@ module RegFile(input wire clk, reset, enable,
// To select a register En input must be 2'b00
decoder d0(
.en(enable),
.index(write_index),
.regOut(decOut)
);
@@ -67,7 +66,7 @@ endmodule
module regFile_tb();
reg [8:0] write_d;
reg [1:0] w_idx, op0_idx, op1_idx;
reg reset,clk, enable;
reg reset,clk;
wire [8:0] op0,op1;
initial begin
@@ -79,7 +78,6 @@ module regFile_tb();
RegFile regFile0(
.clk(clk),
.enable(enable),
.reset(reset),
.write_index(w_idx),
.op0_idx(op0_idx),
@@ -94,7 +92,6 @@ module regFile_tb();
reset = 1;
#5
reset = 0;
enable = 1;
w_idx = 2'b00;
op0_idx = 2'b00;
op1_idx = 2'b00;

280
lab2CA.srcs/sources_1/new/dataMemory.v
View File

@@ -6,24 +6,32 @@ module dataMemory(
output reg [8:0] readData
);
reg [8:0] memory [23:0];
reg [8:0] memory [512:0]; // Maximum of 512 memory locations
// Vivado will give warnings of unconnected ports on the "address" bus if they are unused
initial begin
//Equation Solver Memory
// memory[0] <= 9'b000000001;
// memory[1] <= 9'b000000010;
// String Compare Memory
// memory[0] <= 9'b000000100;
// memory[1] <= 9'b000001000;
// memory[2] <= 9'b000001100;
// memory[3] <= 9'b010101010;
// memory[4] <= 9'b000001111;
// memory[5] <= 9'b000000100;
// memory[6] <= 9'b000000000;
// memory[7] <= 9'b000000111;
// memory[8] <= 9'b000001111;
// memory[9] <= 9'b000000110;
// memory[0] <= 9'b000000100;
// memory[1] <= 9'b000001000;
// memory[2] <= 9'b000001100;
// memory[3] <= 9'b010101010;
// memory[4] <= 9'b000001111;
// memory[5] <= 9'b000000100;
// memory[6] <= 9'b000000000;
// memory[7] <= 9'b000000111;
// memory[8] <= 9'b000001111;
// memory[9] <= 9'b000000110;
// memory[10] <= 9'b000000010;
// memory[11] <= 9'b000000000;
// memory[12] <= 9'b000000000;
@@ -31,34 +39,39 @@ module dataMemory(
// memory[14] <= 9'b000000000;
// memory[15] <= 9'b000000000;
// Bubble Sort Initial Memory
memory[0] <= 9'b000010110;
memory[1] <= 9'b000100010;
memory[2] <= 9'b000100000;
memory[3] <= 9'b010001000;
memory[4] <= 9'b010010000;
memory[5] <= 9'b010011000;
memory[6] <= 9'b101001000;
memory[7] <= 9'b101001010;
memory[8] <= 9'b000100011;
memory[9] <= 9'b101001001;
memory[10] <= 9'b011001001;
memory[11] <= 9'b001001000;
memory[12] <= 9'b101001001;
memory[13] <= 9'b011101000;
memory[14] <= 9'b110001010;
memory[15] <= 9'b000100001;
memory[16] <= 9'b100110100;
memory[17] <= 9'b000001001;
memory[18] <= 9'b011001001;
memory[19] <= 9'b000110010;
memory[20] <= 9'b000000001;
memory[21] <= 9'b000111010;
memory[22] <= 9'b101011110;
memory[23] <= 9'b011111100;
// memory[0] <= 9'b000010110;
// memory[1] <= 9'b000100010;
// memory[2] <= 9'b000100000;
// memory[3] <= 9'b010001000;
// memory[4] <= 9'b010010000;
// memory[5] <= 9'b010011000;
// memory[6] <= 9'b101001000;
// memory[7] <= 9'b101001010;
// memory[8] <= 9'b000100011;
// memory[9] <= 9'b101001001;
// memory[10] <= 9'b011001001;
// memory[11] <= 9'b001001000;
// memory[12] <= 9'b101001001;
// memory[13] <= 9'b011101000;
// memory[14] <= 9'b110001010;
// memory[15] <= 9'b000100001;
// memory[16] <= 9'b100110100;
// memory[17] <= 9'b000001001;
// memory[18] <= 9'b011001001;
// memory[19] <= 9'b000110010;
// memory[20] <= 9'b000000001;
// memory[21] <= 9'b000111010;
// memory[22] <= 9'b101011110;
// memory[23] <= 9'b011111100;
// Binary Search Memory
// memory[0] <= 9'b000000000;
// memory[1] <= 9'b000000111;
// memory[2] <= 9'b000000001;
@@ -79,19 +92,160 @@ module dataMemory(
// memory[17] <= 9'b000010000;
// memory[18] <= 9'b000010001;
// memory[19] <= 9'b000010010;
// Program 1 Test Data
// memory[0] <= 9'd100;
// memory[1] <= 9'd58;
// memory[2] <= 9'd6;
// memory[3] <= 9'd12;
// memory[4] <= 9'b110110000; // -80
// memory[5] <= 9'd17;
// memory[6] <= 9'b111011011; // -37
// memory[7] <= 9'd25;
// memory[8] <= -9'd83; // -83
// memory[9] <= -9'd98; // -98
// memory[10] <= -9'd98; // -98
// memory[11] <= -9'd74; // -74
// memory[12] <= 9'd70;
// memory[13] <= -9'd38; // -38
// memory[14] <= 9'd52;
// memory[15] <= -9'd96; // -96
// memory[16] <= -9'd32; // -32
// memory[17] <= -9'd93; // -93
// memory[18] <= -9'd40; // -40
// memory[19] <= 9'd59;
// memory[20] <= 9'd10;
// memory[21] <= 9'd81;
// memory[22] <= -9'd23; // -28
// memory[23] <=- 9'd99; // -99
// memory[24] <= -9'd41; // -41
// memory[25] <= 9'd33;
// memory[26] <= 9'd98;
// memory[27] <= 9'd73;
// memory[28] <= -9'd1; // -1
// memory[29] <= 9'd28;
// memory[30] <= 9'd5;
// memory[31] <= -9'd74; // -74
// memory[32] <= -9'd41; // -41
// memory[33] <= 9'd41;
// memory[34] <= 9'd39;
// memory[35] <= 9'd62;
// memory[36] <= 9'd19;
// memory[37] <= -9'd40; // -40
// memory[38] <= -9'd8; // -8
// memory[39] <= 9'd92;
// memory[40] <= 9'd37;
// memory[41] <= 9'd50;
// memory[42] <= -9'd72; // -72
// memory[43] <= -9'd5; // -5
// memory[44] <= 9'd19;
// memory[45] <= 9'd58;
// memory[46] <= -9'd13; // -13
// memory[47] <= 9'd0;
// memory[48] <= -9'd97; // -97
// memory[49] <= 9'd54;
// memory[50] <= -9'd17; // -17
// memory[51] <= -9'd83; // -83
// memory[52] <= 9'd53;
// memory[53] <= 9'd82;
// memory[54] <= -9'd94; // -94
// memory[55] <= -9'd77; // -77
// memory[56] <= -9'd74; // -74
// memory[57] <= -9'd52; // -52
// memory[58] <= 9'd85;
// memory[59] <= -9'd65; // -65
// memory[60] <= -9'd10; // -10
// memory[61] <= -9'd45; // -45
// memory[62] <= -9'd92; // -92
// memory[63] <= -9'd30; // -30
// memory[64] <= 9'd18;
// memory[65] <= -9'd95; // -95
// memory[66] <= -9'd27; // -27
// memory[67] <= -9'd74; // -74
// memory[68] <= 9'd62;
// memory[69] <= 9'd64;
// memory[70] <= -9'd9; // -9
// memory[71] <= 9'd66;
// memory[72] <= -9'd71; // -71
// memory[73] <= -9'd31; // -31
// memory[74] <= 9'd34;
// memory[75] <= 9'd12;
// memory[76] <= 9'd3;
// memory[77] <= 9'd82;
// memory[78] <= 9'd13;
// memory[79] <= -9'd78; // -78
// memory[80] <= -9'd8; // -8
// memory[81] <= 9'd88;
// memory[82] <= 9'd42;
// memory[83] <= 9'd42;
// memory[84] <= 9'd21;
// memory[85] <= -9'd44; // -44
// memory[86] <= 9'd30;
// memory[87] <= -9'd93; // -93
// memory[88] <= 9'd2;
// memory[89] <= -9'd34; // -34
// memory[90] <= 9'd92;
// memory[91] <= -9'd45; // -45
// memory[92] <= 9'd26;
// memory[93] <= -9'd79; // -79
// memory[94] <= 9'd43;
// memory[95] <= -9'd25; // -25
// memory[96] <= -9'd24; // -24
// memory[97] <= -9'd25; // -25
// memory[98] <= -9'd19; // -19
// memory[99] <= -9'd49; // -49
// memory[100] <= -9'd8; // -8
// Program 2 Test Data
// memory[0] <= 9'd4;
// memory[1] <= 9'd15;
// memory[2] <= 9'b000001100;
// memory[3] <= 9'b010101010;
// memory[4] <= 9'h68; // h
// memory[5] <= 9'h65; // e
// memory[6] <= 9'h6C; // l
// memory[7] <= 9'h6C; // l
// memory[8] <= 9'h6F; // o
// memory[9] <= 9'h20; // <space>
// memory[10] <= 9'h77; // w
// memory[11] <= 9'h6F; // o
// memory[12] <= 9'h72; // r
// memory[13] <= 9'h6C; // l
// memory[14] <= 9'h64; // d
// memory[15] <= 9'h68; // h
// memory[16] <= 9'h65; // e
// memory[17] <= 9'h6C; // l
// memory[18] <= 9'h6C; // l
// memory[19] <= 9'h6F; // o
// memory[20] <= 9'h20; // <space>
// memory[21] <= 9'h77; // w
// memory[22] <= 9'h6F; // o
// memory[23] <= 9'h72; // r
// memory[24] <= 9'h6C; // l
// memory[25] <= 9'h64; // d
// Program 3 Test Data
// memory[0] <= 9'd25; // 25
// memory[1] <= -9'd3; // -3
end
always@(address, clk, memory)begin
if(clk == 1'b1)begin
readData <= memory[address];
if(writeEnable == 1'b1)begin
memory[address] <= writeData;
end
else begin
memory[address] <= memory[address];
end
end
always @ (posedge clk)
begin
if(writeEnable == 1'b1)
memory[address] <= writeData;
else
readData <= memory[address];
end
endmodule
@@ -100,12 +254,8 @@ module dataMemory_tb();
reg [8:0] address, writeData;
wire [8:0] readData;
initial begin
clk = 1'b0;
end
always begin
always
#5 clk = ~clk; // Period to be determined
end
dataMemory dM0(
.clk(clk),
@@ -115,7 +265,9 @@ module dataMemory_tb();
.readData(readData)
);
initial begin
initial
begin
clk = 1'b0;
writeEnable = 1'b0;
address = 9'b000000000;
writeData = 9'b010101010;
@@ -133,7 +285,27 @@ module dataMemory_tb();
address = 9'b000000010;
writeData = 9'b000000101;
#10
address = 9'b000000011;
writeEnable = 1'b0;
address = 9'b001000000;
writeData = 9'b010101010;
#10
address = 9'b001000001;
writeData = 9'b000001111;
#10
address = 9'b000011010;
writeData = 9'b000000101;
#10
writeEnable = 1'b1;
address = 9'b100111000;
writeData = 9'b010101010;
#10
address = 9'b100100001;
writeData = 9'b000001111;
#10
address = 9'b110000010;
writeData = 9'b000000101;
#10
address = 9'b111110011;
writeData = 9'b000000011;
#10
address = 9'b00000010;

156
lab2CA.srcs/sources_1/new/instructionMemory.v
View File

@@ -1,7 +1,6 @@
`timescale 1ns / 1ps
module instructionMemory(
input wire clk,
input wire [8:0] address,
output reg [8:0] readData
);
@@ -10,15 +9,12 @@ module instructionMemory(
initial begin
//Equation Solver
// memory[0] <= 9'b000000000;
// memory[1] <= 9'b011000000; //add0
// memory[1] <= 9'b011001001; //add1
// memory[1] <= 9'b000100000; //load
// memory[2] <= 9'b000101000; //load
// memory[3] <= 9'b010100010; //add
// memory[4] <= 9'b111100000; //shift left
// memory[5] <= 9'b111100000; //shift left
// memory[6] <= 9'b000000000; //halt
memory[0] <= 9'b000000000;
memory[1] <= 9'b000100000; //load
memory[2] <= 9'b000101000; //load
memory[3] <= 9'b010100010; //add
memory[4] <= 9'b111100000; //shift left
memory[5] <= 9'b111100000; //shift left
// //Testing all instructions
// memory[6] <= 9'b010100011; //sub
@@ -80,68 +76,68 @@ module instructionMemory(
// Bubble Sort
memory[0] <= 9'b000000001; // nop
// Setup
memory[1] <= 9'b010000000; // zero $a
memory[2] <= 9'b000100000; // lb $a, $a
memory[3] <= 9'b010001000; // zero $b
memory[4] <= 9'b010010000; // zero $c
memory[5] <= 9'b010011000; // zero $d
memory[6] <= 9'b101001000; // banks $b, $0
memory[7] <= 9'b101001010; // banks $b, $1
memory[8] <= 9'b100100011; // jf EndChk
// Increment current index to compare next pair of values
// Inc:
memory[9] <= 9'b101001001; // bankl $b, $0
memory[10] <= 9'b011001001; // addi $b, 1
memory[11] <= 9'b101001000; // banks $b, $0
// Check if at the end of the array
// EndChk:
memory[12] <= 9'b101001001; // bankl $b, $0
memory[13] <= 9'b011101000; // slt $b, $a
memory[14] <= 9'b110001001; // beq $b, JSC
memory[15] <= 9'b100100001; // jf LoadNext
// JSC:
memory[16] <= 9'b100110100; // jf SwapChk
// Load next values for comparison
// LoadNext:
memory[17] <= 9'b101001001; // bankl $b, $0
memory[18] <= 9'b011001001; // addi $b, 1
memory[19] <= 9'b000110010; // lb $c, $b
memory[20] <= 9'b011001001; // addi $b, 1
memory[21] <= 9'b000111010; // lb $d, $b
// Compare loaded values to see if they need to be swapped
memory[22] <= 9'b101011110; // banks $d, $3
memory[23] <= 9'b011111100; // slt $d, $c
memory[24] <= 9'b110011001; // beq $d, JI
memory[25] <= 9'b100100001; // jf Swap
// JI:
memory[26] <= 9'b101110010; // jb Inc
// Swap values in array
// Swap:
memory[27] <= 9'b101001001; // bankl $b, $0
memory[28] <= 9'b011001001; // addi $b, 1
memory[29] <= 9'b101011111; // bankl $d, $3
memory[30] <= 9'b001011010; // sb $d, $b
memory[31] <= 9'b011001001; // addi $b, 1
memory[32] <= 9'b001010010; // sb $c, $b
memory[33] <= 9'b010001000; // zero $b
memory[34] <= 9'b011001001; // addi $b, 1
memory[35] <= 9'b101001010; // banks $b, $1
memory[36] <= 9'b101111100; // jb Inc
// Check to see if any swaps have been made in the last iteration
// SwapChk:
memory[37] <= 9'b101001011; // bankl $b, $1
memory[38] <= 9'b110001001; // beq $b, JE
memory[39] <= 9'b100100001; // jf Reset
// JE:
memory[40] <= 9'b100100011; // jf End
// Reset:
memory[41] <= 9'b010001000; // zero $b
memory[42] <= 9'b101001000; // banks $b, $0
memory[43] <= 9'b101111011; // jb LoadNext
// End:
memory[44] <= 9'b000000000; // halt
// memory[0] <= 9'b000000001; // nop
// // Setup
// memory[1] <= 9'b010000000; // zero $a
// memory[2] <= 9'b000100000; // lb $a, $a
// memory[3] <= 9'b010001000; // zero $b
// memory[4] <= 9'b010010000; // zero $c
// memory[5] <= 9'b010011000; // zero $d
// memory[6] <= 9'b101001000; // banks $b, $0
// memory[7] <= 9'b101001010; // banks $b, $1
// memory[8] <= 9'b100100011; // jf EndChk
// // Increment current index to compare next pair of values
// // Inc:
// memory[9] <= 9'b101001001; // bankl $b, $0
// memory[10] <= 9'b011001001; // addi $b, 1
// memory[11] <= 9'b101001000; // banks $b, $0
// // Check if at the end of the array
// // EndChk:
// memory[12] <= 9'b101001001; // bankl $b, $0
// memory[13] <= 9'b011101000; // slt $b, $a
// memory[14] <= 9'b110001001; // beq $b, JSC
// memory[15] <= 9'b100100001; // jf LoadNext
// // JSC:
// memory[16] <= 9'b100110100; // jf SwapChk
// // Load next values for comparison
// // LoadNext:
// memory[17] <= 9'b101001001; // bankl $b, $0
// memory[18] <= 9'b011001001; // addi $b, 1
// memory[19] <= 9'b000110010; // lb $c, $b
// memory[20] <= 9'b011001001; // addi $b, 1
// memory[21] <= 9'b000111010; // lb $d, $b
// // Compare loaded values to see if they need to be swapped
// memory[22] <= 9'b101011110; // banks $d, $3
// memory[23] <= 9'b011111100; // slt $d, $c
// memory[24] <= 9'b110011001; // beq $d, JI
// memory[25] <= 9'b100100001; // jf Swap
// // JI:
// memory[26] <= 9'b101110010; // jb Inc
// // Swap values in array
// // Swap:
// memory[27] <= 9'b101001001; // bankl $b, $0
// memory[28] <= 9'b011001001; // addi $b, 1
// memory[29] <= 9'b101011111; // bankl $d, $3
// memory[30] <= 9'b001011010; // sb $d, $b
// memory[31] <= 9'b011001001; // addi $b, 1
// memory[32] <= 9'b001010010; // sb $c, $b
// memory[33] <= 9'b010001000; // zero $b
// memory[34] <= 9'b011001001; // addi $b, 1
// memory[35] <= 9'b101001010; // banks $b, $1
// memory[36] <= 9'b101111100; // jb Inc
// // Check to see if any swaps have been made in the last iteration
// // SwapChk:
// memory[37] <= 9'b101001011; // bankl $b, $1
// memory[38] <= 9'b110001001; // beq $b, JE
// memory[39] <= 9'b100100001; // jf Reset
// // JE:
// memory[40] <= 9'b100100011; // jf End
// // Reset:
// memory[41] <= 9'b010001000; // zero $b
// memory[42] <= 9'b101001000; // banks $b, $0
// memory[43] <= 9'b101111011; // jb LoadNext
// // End:
// memory[44] <= 9'b000000000; // halt
// Binary Search
@@ -213,28 +209,16 @@ module instructionMemory(
end
always@(address, clk)begin
if(clk == 1'b1)begin
readData <= memory[address];
end
end
always @ (address)
readData <= memory[address];
endmodule
module instructionMemory_tb();
reg clk;
reg [8:0] address;
wire [8:0] readData;
initial begin
clk = 1'b0;
end
always begin
#5 clk = ~clk; // Period to be determined
end
instructionMemory iM0(
.clk(clk),
.address(address),
.readData(readData)
);

17
lab2CA.xpr
View File

@@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="39" Path="C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr">
<Project Version="7" Minor="39" Path="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="0a5803efda44405bb28bbf43ba22e808"/>
@@ -31,7 +31,7 @@
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="341"/>
<Option Name="WTXSimLaunchSim" Val="343"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -123,14 +123,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../Downloads/pipeline_example.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="CPU9bits"/>
@@ -156,7 +148,7 @@
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="CPU9bits_tb"/>
<Option Name="TopModule" Val="CPU9bits"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
@@ -202,7 +194,7 @@
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k160tifbg484-2L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k160tifbg484-2L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
@@ -215,6 +207,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>