Update
This commit is contained in:
Johannes
Binary file not shown.
@@ -17,7 +17,6 @@ proc create_report { reportName command } {
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send_msg_id runtcl-5 warning "$msg"
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}
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}
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set_param synth.incrementalSynthesisCache C:/Users/willi/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-18452-WM-G75VW/incrSyn
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set_msg_config -id {Synth 8-256} -limit 10000
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set_msg_config -id {Synth 8-638} -limit 10000
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create_project -in_memory -part xc7k160tifbg484-2L
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@@ -2,8 +2,8 @@
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# Vivado v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Sun Mar 24 16:57:48 2019
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# Process ID: 9320
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# Start of session at: Sat Mar 30 15:52:45 2019
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# Process ID: 9028
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# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1
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# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
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# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
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@@ -15,115 +15,87 @@ Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 4932
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WARNING: [Synth 8-1958] event expressions must result in a singular type [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:81]
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INFO: Helper process launched with PID 18388
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---------------------------------------------------------------------------------
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Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 376.207 ; gain = 113.672
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Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 364.258 ; gain = 100.730
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---------------------------------------------------------------------------------
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INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
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INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
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WARNING: [Synth 8-567] referenced signal 'writeEnable' should be on the sensitivity list [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:81]
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WARNING: [Synth 8-567] referenced signal 'writeData' should be on the sensitivity list [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:81]
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INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
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INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
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INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:266]
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INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
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INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
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INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
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INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412]
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INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
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INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:766]
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INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:766]
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INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:396]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:401]
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INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:396]
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INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
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INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
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INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
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INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342]
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INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
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INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:325]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:331]
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INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:325]
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INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
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INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
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INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
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INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
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INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
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INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
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INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
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INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
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INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
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INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
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INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
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INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1300]
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INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1365]
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INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:676]
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INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:676]
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INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1365]
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INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1300]
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INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:713]
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INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:713]
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INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:632]
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INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:632]
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INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
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INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
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INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
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INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
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INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
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INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
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INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
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INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
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INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
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INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
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INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
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INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
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INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541]
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INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
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WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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WARNING: [Synth 8-3848] Net result_O in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:842]
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INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:842]
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INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:916]
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INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:916]
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INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:879]
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INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:879]
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INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:309]
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INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:309]
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INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1414]
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INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1414]
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INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:524]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:530]
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INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:524]
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INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
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INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:17]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:13]
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INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996]
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INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996]
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INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
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INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356]
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INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
|
||||
INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:985]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:985]
|
||||
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:339]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:345]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:339]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (27#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
|
||||
WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0]
|
||||
WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0]
|
||||
WARNING: [Synth 8-3331] design shift_left has unconnected port A[8]
|
||||
WARNING: [Synth 8-3331] design instructionMemory has unconnected port clk
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 414.008 ; gain = 151.473
|
||||
Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 420.883 ; gain = 157.355
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 414.008 ; gain = 151.473
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 420.883 ; gain = 157.355
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k160tifbg484-2L
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 420.883 ; gain = 157.355
|
||||
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 414.008 ; gain = 151.473
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[15]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[14]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[13]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[12]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[11]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[10]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[9]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[8]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[7]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[6]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[5]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[4]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[3]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[2]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[1]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[0]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'dataMemEn_reg' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:26]
|
||||
INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 461.227 ; gain = 198.691
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 420.883 ; gain = 157.355
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-223] decloning instance 'SE1' (sign_extend_3bit) to 'SE3'
|
||||
|
||||
@@ -140,18 +112,21 @@ Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 162
|
||||
+---Registers :
|
||||
9 Bit Registers := 9
|
||||
9 Bit Registers := 10
|
||||
+---RAMs :
|
||||
4K Bit RAMs := 1
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 28
|
||||
4 Input 9 Bit Muxes := 4
|
||||
2 Input 4 Bit Muxes := 2
|
||||
7 Input 9 Bit Muxes := 1
|
||||
4 Input 9 Bit Muxes := 5
|
||||
2 Input 9 Bit Muxes := 8
|
||||
4 Input 4 Bit Muxes := 2
|
||||
16 Input 4 Bit Muxes := 1
|
||||
2 Input 3 Bit Muxes := 2
|
||||
16 Input 3 Bit Muxes := 1
|
||||
16 Input 2 Bit Muxes := 1
|
||||
16 Input 1 Bit Muxes := 24
|
||||
2 Input 1 Bit Muxes := 33
|
||||
8 Input 2 Bit Muxes := 1
|
||||
16 Input 1 Bit Muxes := 7
|
||||
2 Input 1 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
@@ -159,16 +134,24 @@ Finished RTL Component Statistics
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module dataMemory
|
||||
Module CPU9bits
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 20
|
||||
16 Input 1 Bit Muxes := 16
|
||||
2 Input 1 Bit Muxes := 32
|
||||
4 Input 9 Bit Muxes := 1
|
||||
8 Input 2 Bit Muxes := 1
|
||||
Module instructionMemory
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
7 Input 9 Bit Muxes := 1
|
||||
Module dataMemory
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
+---RAMs :
|
||||
4K Bit RAMs := 1
|
||||
Module decoder
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 4 Bit Muxes := 1
|
||||
4 Input 4 Bit Muxes := 1
|
||||
Module register
|
||||
Detailed RTL Component Info :
|
||||
@@ -193,7 +176,7 @@ Detailed RTL Component Info :
|
||||
2 Input 3 Bit Muxes := 2
|
||||
16 Input 3 Bit Muxes := 1
|
||||
16 Input 2 Bit Muxes := 1
|
||||
16 Input 1 Bit Muxes := 8
|
||||
16 Input 1 Bit Muxes := 7
|
||||
Module bit1_mux_2_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
@@ -216,23 +199,24 @@ Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP and Shift Register Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
ROM:
|
||||
+------------------+------------+---------------+----------------+
|
||||
|Module Name | RTL Object | Depth x Width | Implemented As |
|
||||
+------------------+------------+---------------+----------------+
|
||||
|instructionMemory | p_0_out | 64x9 | LUT |
|
||||
|CPU9bits | p_0_out | 64x9 | LUT |
|
||||
+------------------+------------+---------------+----------------+
|
||||
Block RAM: Preliminary Mapping Report (see note below)
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|dataMemory: | memory_reg | 512 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|
||||
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished ROM, RAM, DSP and Shift Register Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6837] The timing for the instance i_1/dM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
@@ -244,7 +228,21 @@ No constraint files found.
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP and Shift Register Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Block RAM: Final Mapping Report
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|dataMemory: | memory_reg | 512 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
Finished ROM, RAM, DSP and Shift Register Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -255,8 +253,9 @@ Report RTL Partitions:
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6837] The timing for the instance dM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -280,7 +279,7 @@ Start Final Netlist Cleanup
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
@@ -293,7 +292,7 @@ Report Check Netlist:
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -305,25 +304,25 @@ Report RTL Partitions:
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
@@ -336,65 +335,55 @@ Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+------+------+
|
||||
| |Cell |Count |
|
||||
+------+------+------+
|
||||
|1 |BUFG | 2|
|
||||
|2 |LUT2 | 45|
|
||||
|3 |LUT3 | 50|
|
||||
|4 |LUT4 | 51|
|
||||
|5 |LUT5 | 69|
|
||||
|6 |LUT6 | 439|
|
||||
|7 |MUXF7 | 6|
|
||||
|8 |FDRE | 81|
|
||||
|9 |LD | 154|
|
||||
|10 |IBUF | 2|
|
||||
|11 |OBUF | 1|
|
||||
+------+------+------+
|
||||
+------+---------+------+
|
||||
| |Cell |Count |
|
||||
+------+---------+------+
|
||||
|1 |BUFG | 1|
|
||||
|2 |LUT2 | 4|
|
||||
|3 |LUT3 | 3|
|
||||
|4 |LUT4 | 27|
|
||||
|5 |LUT5 | 10|
|
||||
|6 |LUT6 | 37|
|
||||
|7 |RAMB18E1 | 1|
|
||||
|8 |FDRE | 21|
|
||||
|9 |IBUF | 2|
|
||||
|10 |OBUF | 10|
|
||||
+------+---------+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+------------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+------------+------+
|
||||
|1 |top | | 900|
|
||||
|2 | Bank |RegFile | 45|
|
||||
|3 | r0 |register_5 | 16|
|
||||
|4 | r1 |register_6 | 9|
|
||||
|5 | r2 |register_7 | 10|
|
||||
|6 | r3 |register_8 | 10|
|
||||
|7 | CU |ControlUnit | 14|
|
||||
|8 | FetchU |FetchUnit | 126|
|
||||
|9 | PC |register_4 | 126|
|
||||
|10 | RF |RegFile_0 | 345|
|
||||
|11 | r0 |register | 216|
|
||||
|12 | r1 |register_1 | 14|
|
||||
|13 | r2 |register_2 | 100|
|
||||
|14 | r3 |register_3 | 15|
|
||||
|15 | dM |dataMemory | 365|
|
||||
+------+---------+------------+------+
|
||||
+------+---------+-----------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-----------+------+
|
||||
|1 |top | | 116|
|
||||
|2 | FetchU |FetchUnit | 31|
|
||||
|3 | PC |register_1 | 31|
|
||||
|4 | RF |RegFile | 71|
|
||||
|5 | r0 |register | 42|
|
||||
|6 | r1 |register_0 | 29|
|
||||
|7 | dM |dataMemory | 1|
|
||||
+------+---------+-----------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 29 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 160 Unisim elements for replacement
|
||||
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 723.004 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 684.082 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 154 instances were transformed.
|
||||
LD => LDCE: 154 instances
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
70 Infos, 29 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
73 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 723.004 ; gain = 473.363
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 723.004 ; gain = 0.000
|
||||
synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 684.082 ; gain = 433.695
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 684.082 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Sun Mar 24 16:58:31 2019...
|
||||
INFO: [Common 17-206] Exiting Vivado at Sat Mar 30 15:53:22 2019...
|
||||
|
||||
Binary file not shown.
@@ -1,951 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Sun Mar 24 18:28:31 2019
|
||||
# Process ID: 5228
|
||||
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
|
||||
# Command line: vivado.exe -log CPU9bits_tb.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl
|
||||
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.vds
|
||||
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source CPU9bits_tb.tcl -notrace
|
||||
Command: synth_design -top CPU9bits_tb -part xc7k160tifbg484-2L
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 14244
|
||||
WARNING: [Synth 8-1958] event expressions must result in a singular type [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:85]
|
||||
---------------------------------------------------------------------------------
|
||||
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 372.199 ; gain = 114.445
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'CPU9bits_tb' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:172]
|
||||
WARNING: [Synth 8-85] always block has no event control specified [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:179]
|
||||
INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
|
||||
WARNING: [Synth 8-567] referenced signal 'writeEnable' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:85]
|
||||
WARNING: [Synth 8-567] referenced signal 'writeData' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:85]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
|
||||
INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
|
||||
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
|
||||
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
|
||||
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
|
||||
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
|
||||
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
|
||||
INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
|
||||
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
|
||||
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
|
||||
WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
WARNING: [Synth 8-3848] Net result_O in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:17]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996]
|
||||
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (27#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits_tb' (28#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:172]
|
||||
WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0]
|
||||
WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0]
|
||||
WARNING: [Synth 8-3331] design shift_left has unconnected port A[8]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Synthesize : Time (s): cpu = 00:01:51 ; elapsed = 00:01:54 . Memory (MB): peak = 2338.125 ; gain = 2080.371
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:02:04 ; elapsed = 00:02:09 . Memory (MB): peak = 2338.125 ; gain = 2080.371
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k160tifbg484-2L
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:02:04 ; elapsed = 00:02:09 . Memory (MB): peak = 2338.125 ; gain = 2080.371
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
|
||||
INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[511]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[510]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[509]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[508]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[507]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[506]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[505]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[504]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[503]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[502]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[501]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[500]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[499]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[498]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[497]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[496]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[495]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[494]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[493]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[492]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[491]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[490]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[489]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[488]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[487]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[486]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[485]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[484]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[483]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[482]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[481]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[480]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[479]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[478]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[477]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[476]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[475]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[474]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[473]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[472]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[471]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[470]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[469]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[468]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[467]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[466]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[465]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[464]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[463]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[462]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[461]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[460]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[459]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[458]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[457]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[456]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[455]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[454]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[453]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[452]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[451]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[450]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[449]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[448]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[447]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[446]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[445]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[444]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[443]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[442]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[441]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[440]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[439]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[438]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[437]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[436]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[435]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[434]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[433]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[432]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[431]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[430]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[429]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[428]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[427]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[426]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[425]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[424]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[423]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[422]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[421]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[420]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[419]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[418]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[417]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[416]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[415]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[414]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[413]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[412]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:202]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[511]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[510]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[509]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[508]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[507]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[506]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[505]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[504]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[503]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[502]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[501]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[500]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[499]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[498]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[497]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[496]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[495]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[494]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[493]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[492]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[491]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[490]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[489]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[488]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[487]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[486]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[485]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[484]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[483]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[482]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[481]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[480]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[479]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[478]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[477]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[476]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[475]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[474]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[473]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[472]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[471]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[470]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[469]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[468]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[467]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[466]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[465]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[464]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[463]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[462]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[461]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[460]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[459]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[458]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[457]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[456]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[455]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[454]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[453]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[452]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[451]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[450]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[449]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[448]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[447]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[446]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[445]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[444]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[443]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[442]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[441]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[440]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[439]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[438]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[437]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[436]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[435]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[434]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[433]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[432]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[431]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[430]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[429]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[428]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[427]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[426]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[425]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[424]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[423]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[422]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[421]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[420]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[419]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[418]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[417]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[416]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[415]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[414]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
|
||||
INFO: [Common 17-14] Message 'Synth 8-327' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:04:25 ; elapsed = 00:04:33 . Memory (MB): peak = 2906.012 ; gain = 2648.258
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-223] decloning instance 'CPU9bits0/SE1' (sign_extend_3bit) to 'CPU9bits0/SE3'
|
||||
|
||||
Report RTL Partitions:
|
||||
+------+----------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+------+----------------+------------+----------+
|
||||
|1 |dataMemory__GB0 | 1| 2378380|
|
||||
|2 |CPU9bits__GC0 | 1| 1169|
|
||||
+------+----------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 162
|
||||
+---Registers :
|
||||
9 Bit Registers := 9
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 520
|
||||
8 Input 9 Bit Muxes := 1
|
||||
4 Input 9 Bit Muxes := 4
|
||||
2 Input 4 Bit Muxes := 2
|
||||
4 Input 4 Bit Muxes := 2
|
||||
16 Input 4 Bit Muxes := 1
|
||||
2 Input 3 Bit Muxes := 2
|
||||
16 Input 3 Bit Muxes := 1
|
||||
16 Input 2 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 513
|
||||
16 Input 1 Bit Muxes := 8
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module dataMemory
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 512
|
||||
2 Input 1 Bit Muxes := 512
|
||||
Module instructionMemory
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
8 Input 9 Bit Muxes := 1
|
||||
Module decoder__1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 4 Bit Muxes := 1
|
||||
4 Input 4 Bit Muxes := 1
|
||||
Module register__8
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
Module register__7
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
Module register__6
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
Module register__5
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
Module mux_4_1__3
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
4 Input 9 Bit Muxes := 1
|
||||
Module mux_4_1__2
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
4 Input 9 Bit Muxes := 1
|
||||
Module decoder
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 4 Bit Muxes := 1
|
||||
4 Input 4 Bit Muxes := 1
|
||||
Module register__2
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
Module register__3
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
Module register__4
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
Module register
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
Module mux_4_1__1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
4 Input 9 Bit Muxes := 1
|
||||
Module mux_4_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
4 Input 9 Bit Muxes := 1
|
||||
Module register__1
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
Module add_1bit__44
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__43
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__42
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__41
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__40
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__39
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__38
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__37
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__36
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module mux_2_1__1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 1
|
||||
Module add_1bit__35
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__34
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__33
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__32
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__31
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__30
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__29
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__28
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__27
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__62
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__61
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__60
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__59
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__58
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__57
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__56
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__55
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__54
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__26
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__25
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__24
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__23
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__22
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__21
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__20
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__19
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__18
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__80
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__79
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__78
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__77
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__76
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__75
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__74
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__73
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__72
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__71
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__70
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__69
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__68
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__67
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__66
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__65
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__64
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__63
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module ControlUnit
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
16 Input 4 Bit Muxes := 1
|
||||
2 Input 3 Bit Muxes := 2
|
||||
16 Input 3 Bit Muxes := 1
|
||||
16 Input 2 Bit Muxes := 1
|
||||
16 Input 1 Bit Muxes := 8
|
||||
Module add_1bit__53
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__52
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__51
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__50
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__49
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__48
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__47
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__46
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__45
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module mux_2_1__2
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 1
|
||||
Module add_1bit__17
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__16
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__15
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__14
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__13
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__12
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__11
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__10
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__9
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module mux_2_1__3
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 1
|
||||
Module mux_2_1__4
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 1
|
||||
Module bit1_mux_2_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module add_1bit__1
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__2
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__3
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__4
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__5
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__6
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__7
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit__8
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module add_1bit
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module mux_2_1__5
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 1
|
||||
Module mux_2_1__6
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 1
|
||||
Module mux_2_1__7
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 1
|
||||
Module mux_2_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 600 (col length:100)
|
||||
BRAMs: 650 (col length: RAMB18 100 RAMB36 50)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
INFO: [Synth 8-3886] merging instance 'CPU9bits0i_1/iM/readData_reg[0]' (LD) to 'CPU9bits0i_1/iM/readData_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'CPU9bits0i_1/iM/readData_reg[8]' (LD) to 'CPU9bits0i_1/iM/readData_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'CPU9bits0i_1/iM/readData_reg[2]' (LD) to 'CPU9bits0i_1/iM/readData_reg[4]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\iM/readData_reg[4] )
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:09:23 ; elapsed = 00:09:37 . Memory (MB): peak = 3340.348 ; gain = 3082.594
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:09:23 ; elapsed = 00:09:37 . Memory (MB): peak = 3340.348 ; gain = 3082.594
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:09:23 ; elapsed = 00:09:37 . Memory (MB): peak = 3340.348 ; gain = 3082.594
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+-+-----+------+
|
||||
| |Cell |Count |
|
||||
+-+-----+------+
|
||||
+-+-----+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+-------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-------+------+
|
||||
|1 |top | | 0|
|
||||
+------+---------+-------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 526 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3340.348 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
177 Infos, 111 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:09:36 ; elapsed = 00:10:01 . Memory (MB): peak = 3340.348 ; gain = 3090.086
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 3340.348 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_tb_utilization_synth.rpt -pb CPU9bits_tb_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Sun Mar 24 18:38:37 2019...
|
||||
Binary file not shown.
Binary file not shown.
@@ -1,7 +1,7 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-----------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Sun Mar 24 16:58:30 2019
|
||||
| Date : Sat Mar 30 15:53:22 2019
|
||||
| Host : WM-G75VW running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
||||
| Design : CPU9bits
|
||||
@@ -30,13 +30,13 @@ Table of Contents
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 578 | 0 | 101400 | 0.57 |
|
||||
| LUT as Logic | 578 | 0 | 101400 | 0.57 |
|
||||
| Slice LUTs* | 73 | 0 | 101400 | 0.07 |
|
||||
| LUT as Logic | 73 | 0 | 101400 | 0.07 |
|
||||
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
|
||||
| Slice Registers | 235 | 0 | 202800 | 0.12 |
|
||||
| Register as Flip Flop | 81 | 0 | 202800 | 0.04 |
|
||||
| Register as Latch | 154 | 0 | 202800 | 0.08 |
|
||||
| F7 Muxes | 6 | 0 | 50700 | 0.01 |
|
||||
| Slice Registers | 21 | 0 | 202800 | 0.01 |
|
||||
| Register as Flip Flop | 21 | 0 | 202800 | 0.01 |
|
||||
| Register as Latch | 0 | 0 | 202800 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
@@ -55,22 +55,23 @@ Table of Contents
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 154 | Yes | - | Reset |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 81 | Yes | Reset | - |
|
||||
| 21 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 325 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 650 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0.5 | 0 | 325 | 0.15 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
|
||||
| RAMB18 | 1 | 0 | 650 | 0.15 |
|
||||
| RAMB18E1 only | 1 | | | |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
@@ -90,7 +91,7 @@ Table of Contents
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 3 | 0 | 285 | 1.05 |
|
||||
| Bonded IOB | 12 | 0 | 285 | 4.21 |
|
||||
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
|
||||
@@ -117,7 +118,7 @@ Table of Contents
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 2 | 0 | 32 | 6.25 |
|
||||
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
|
||||
| BUFIO | 0 | 0 | 32 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
@@ -151,17 +152,16 @@ Table of Contents
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| LUT6 | 439 | LUT |
|
||||
| LDCE | 154 | Flop & Latch |
|
||||
| FDRE | 81 | Flop & Latch |
|
||||
| LUT5 | 69 | LUT |
|
||||
| LUT4 | 51 | LUT |
|
||||
| LUT3 | 50 | LUT |
|
||||
| LUT2 | 45 | LUT |
|
||||
| MUXF7 | 6 | MuxFx |
|
||||
| LUT6 | 37 | LUT |
|
||||
| LUT4 | 27 | LUT |
|
||||
| FDRE | 21 | Flop & Latch |
|
||||
| OBUF | 10 | IO |
|
||||
| LUT5 | 10 | LUT |
|
||||
| LUT2 | 4 | LUT |
|
||||
| LUT3 | 3 | LUT |
|
||||
| IBUF | 2 | IO |
|
||||
| BUFG | 2 | Clock |
|
||||
| OBUF | 1 | IO |
|
||||
| RAMB18E1 | 1 | Block Memory |
|
||||
| BUFG | 1 | Clock |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
@@ -1,9 +1,12 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1553461063">
|
||||
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1553975560">
|
||||
<File Type="PA-TCL" Name="CPU9bits.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="CPU9bits_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="CPU9bits.vds"/>
|
||||
<File Type="RDS-DCP" Name="CPU9bits.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="CPU9bits_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="CPU9bits_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.v">
|
||||
|
||||
@@ -6,4 +6,4 @@ REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log CPU9bits_tb.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl
|
||||
vivado -log CPU9bits.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
|
||||
|
||||
@@ -2,8 +2,8 @@
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Sun Mar 24 16:57:48 2019
|
||||
# Process ID: 9320
|
||||
# Start of session at: Sat Mar 30 15:52:45 2019
|
||||
# Process ID: 9028
|
||||
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1
|
||||
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
|
||||
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
|
||||
|
||||
Binary file not shown.
Reference in New Issue
Block a user