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Johannes
2019-04-06 13:16:35 -04:00
parent 2746d6d49c 443d01eba1
commit f34b3d4098
81 changed files with 3467 additions and 1777 deletions
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20
lab2CA.srcs/sources_1/new/ALU.v
View File

@@ -10,8 +10,8 @@ module ALU(
// Wires for connecting the modules to the mux
wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H,result_I,result_J,result_K,result_L,result_M,result_N,result_O,result_P;
wire cout;
// A (0000) - Add
// A (0000) - Add
add_9bit add0(
.A(operand0),
.B(operand1),
@@ -41,15 +41,15 @@ module ALU(
.C(result_E));
// F (0101) - Shift Left
shift_left sl(
.A(operand0),
.A(operand0[7:0]),
.B(result_F));
// G (0110) - Shift Right Logical
shift_right_logical srl(
.A(operand0),
.A(operand0[8:1]),
.B(result_G));
// H (0111) - Shift Right Arithmetic
shift_right_arithmetic sra(
.A(operand0),
.A(operand0[8:1]),
.B(result_H));
// I (1000) - NOT
not_9bit not0(
@@ -65,8 +65,6 @@ module ALU(
.A(operand0),
.B(result_K));
// L (1011)
// Will hacked in here
// M (1100)
// N (1101)
// O (1110)
@@ -87,10 +85,10 @@ module ALU(
.J(result_J),
.K(result_K),
.L(9'b000000000),
.M(result_M),
.N(result_N),
.O(result_O),
.P(result_P),
.M(9'b111111111), // Currently not used
.N(9'b111111111), // Currently not used
.O(9'b111111111), // Currently not used
.P(9'b111111111), // Currently not used
.out(result));

55
lab2CA.srcs/sources_1/new/BasicModules.v
View File

@@ -259,43 +259,32 @@ module comparator_tb();
endmodule
module decoder (
input wire en,
input wire [1:0] index,
output reg [3:0] regOut);
always @(en, index)begin
if(en == 0)begin
case(index)
2'b00: regOut <= 4'b1110;
2'b01: regOut <= 4'b1101;
2'b10: regOut <= 4'b1011;
2'b11: regOut <= 4'b0111;
default: regOut <= 4'b1111;
endcase
end
else begin
regOut <= 4'b1111;
end
end
always @ (index)
case(index)
2'b00: regOut <= 4'b1110;
2'b01: regOut <= 4'b1101;
2'b10: regOut <= 4'b1011;
2'b11: regOut <= 4'b0111;
default: regOut <= 4'b1111;
endcase
endmodule
//testbench
module decoder_tb();
reg enable;
reg [1:0] indexIn;
wire [3:0] regOut;
decoder dec0(
.en(enable),
.index(indexIn),
.regOut(regOut));
.regOut(regOut)
);
initial begin
enable = 0;
indexIn = 2'b00;
#5
enable = 1;
#5
indexIn = 2'b01;
#5
indexIn = 2'b10;
@@ -885,7 +874,7 @@ module eMPipReg(
endmodule
module shift_left(
input wire [8:0] A,
input wire [7:0] A,
output wire [8:0] B);
assign B = {A[7:0],1'b0};
@@ -921,20 +910,20 @@ module shift_left_tb();
end
endmodule
module shift_right_logical(
input wire [8:0] A,
module shift_right_arithmetic(
input wire [8:1] A,
output wire [8:0] B);
assign B = {1'b0,A[8:1]};
assign B = {A[8],A[8:1]};
endmodule
//testbench
module shift_right_logical_tb();
module shift_right_arithmetic_tb();
reg [8:0] a;
wire [8:0] b;
shift_right_logical tb0(
shift_right_arithmetic tb0(
.A(a),
.B(b));
@@ -958,21 +947,21 @@ module shift_right_logical_tb();
end
endmodule
module shift_right_arithmetic(
input wire [8:0] A,
module shift_right_logical(
input wire [8:1] A,
output wire [8:0] B);
assign B = {A[8],A[8:1]};
assign B = {1'b0,A[8:1]};
endmodule
//testbench
module shift_right_arithmetic_tb();
module shift_right_logical_tb();
reg [8:0] a;
wire [8:0] b;
shift_right_arithmetic tb0(
shift_right_logical tb0(
.A(a),
.B(b));

153
lab2CA.srcs/sources_1/new/CPU9bits.v
View File

@@ -2,33 +2,32 @@
module CPU9bits(
input wire reset, clk,
output reg [8:0] result,
output wire done
);
wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N, bankData, bankOP,jumpNeg;
wire [2:0] FU;
wire [3:0] aluOp;
wire [2:0] FU;
wire [1:0] bankS;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link, js, dataMemEn;
instructionMemory iM(
.clk(clk),
.address(PCout),
.readData(instr)
);
);
dataMemory dM(
.clk(clk),
.writeEnable(dataMemEn),
.writeData(op0),
.address(op1),
.readData(dataMemOut)
);
);
RegFile RF(
.clk(clk),
.reset(reset),
.enable(RegEn),
.write_index(instr[4:3]),
.op0_idx(instr[4:3]),
.op1_idx(instr[2:1]),
@@ -36,11 +35,10 @@ module CPU9bits(
.op0(op0),
.op1(op1)
);
RegFile Bank(
.clk(clk),
.reset(reset),
.enable(bankS[1]),
.write_index(instr[2:1]),
.op0_idx(instr[2:1]),
.op1_idx(2'b00),//Doesn't matter
@@ -48,23 +46,23 @@ module CPU9bits(
.op0(bankOP),
.op1()
);
FetchUnit FetchU(
.clk(clk),
.reset(reset),
.op_idx(fetchBranch),
.AddrIn(FUAddr),
.AddrOut(PCout)
);
ALU alu(
);
ALU alu(
.opcode(aluOp),
.operand0(op0),
.operand1(op1),
.result(AluOut)
);
ControlUnit CU(
);
ControlUnit CU(
.instIn(instr[8:5]),
.functBit(instr[0]),
.aluOut(aluOp),
@@ -77,108 +75,136 @@ module CPU9bits(
.link(link),
.bank(bankS),
.js(js)
);
);
//-----------------------Fetch Unit Stuff
add_9bit JBAdder(
add_9bit JBAdder(
.A(PCout),
.B(JBRes),
.Cin(1'b0),
.Sum(FUJB),
.Cout(cout0));
.Cout(cout0)
);
mux_2_1 mux0(
.A(op0),
.B(FUJB),
.out(FUAddr),
.switch(FU[1]));
twos_compliment_9bit two_comp0(
.switch(FU[1])
);
twos_compliment_9bit two_comp0(
.A({4'b0000,instr[4:0]}),
.B(jumpNeg));
.B(jumpNeg)
);
mux_2_1 mux1(
.A({4'b0000,instr[4:0]}),
.B(jumpNeg),
.out(SE2N),
.switch(js));
.switch(js)
);
mux_2_1 mux2(
.A(SE2N), //Jump -- Change with signer module!
.B(SE1N),//Branch -- Change with signer module!
.out(JBRes),
.switch(FU[2]));
.switch(FU[2])
);
sign_extend_3bit SE1(
.A(instr[2:0]),
.B(SE1N));
.B(SE1N)
);
bit1_mux_2_1 BranMux( // BEQ MUX
.A(FU[0]),
.B(AluOut[0]),
.out(fetchBranch),
.switch(FU[2])); // FU[2] only goes high when BEQ
.switch(FU[2]) // FU[2] only goes high when BEQ
);
///--------------------------Addi Stuff
add_9bit Addier(
.A(SE3N), // Change with signer module!
.B(op0),
.Cin(1'b0),
.Sum(AddiOut),
.Cout(cout1));
.Cout(cout1)
);
sign_extend_3bit SE3(
.A(instr[2:0]),
.B(SE3N));
.B(SE3N)
);
mux_2_1 mux3(
.A(AluOut),
.B(AddiOut),
.out(loadMux),
.switch(addiS));
.switch(addiS)
);
///--------------------------Mem stuff
mux_2_1 mux4(
.A(linkData),
.B(dataMemOut), // This is DATA MEM
.out(bankData),
.switch(loadS));
.switch(loadS)
);
///--------------------------Bank stuff
mux_2_1 mux5(
.A(bankData),
.B(bankOP),
.out(RFIn),
.switch(bankS[0]));
.switch(bankS[0])
);
///--------------------------Link Stuff
mux_2_1 mux6(
.A(loadMux),
.B(PCout),
.out(linkData),
.switch(link));
.switch(link)
);
always @ (instr, dataMemOut, AluOut, AddiOut)
begin
case(instr[8:5])
4'b0001: // Load Byte
result <= dataMemOut;
4'b0101: // Add/Subtract
result <= AluOut;
4'b0110: // Add Immediate
result <= AddiOut;
4'b0111: // Set if Less Than
result <= AluOut;
4'b1101: // NOR
result <= AluOut;
4'b1110: // OR/AND
result <= AluOut;
4'b1111: // Shift Right Logical/Shift Left Logical
result <= AluOut;
default:
result <= 9'bXXXXXXXXX;
endcase
end
endmodule
module CPU9bits_tb();
reg clk, reset;
wire done;
initial begin
clk = 1'b0;
end
always begin
always
#5 clk = ~clk; // Period to be determined
end
CPU9bits CPU9bits0(
.reset(reset),
@@ -186,6 +212,7 @@ module CPU9bits_tb();
.done(done));
initial begin
clk = 1'b0;
#5
reset = 1'b1;
#10

524
lab2CA.srcs/sources_1/new/ControlUnit.v
View File

@@ -5,270 +5,286 @@ module ControlUnit(
input wire functBit,
output reg [3:0] aluOut,
output reg [2:0] FU,
output reg addi,
output reg mem, dataMemEn,
output reg RegEn,
output reg halt,
output reg link,
output reg [1:0] bank,
output reg js);
output reg addi, mem, dataMemEn, RegEn, halt, link, js);
always @(instIn, functBit)begin
case(instIn)
4'b0101:
if(functBit == 1) begin
aluOut <= 4'b0001; //sub
RegEn <= 1'b0;
FU <= 3'b001;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
else begin
aluOut <= 4'b0000; //Add
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1101: begin
aluOut <= 4'b0011; //nor
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0100: begin
aluOut <= 4'b1011; //zero
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1110:
if(functBit == 1) begin
aluOut <= 4'b0100; //and
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
else begin
aluOut <= 4'b0010; //or
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1111:
if(functBit == 1) begin
aluOut <= 4'b0110; //srl
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
else begin
aluOut <= 4'b0101; //shift left
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0111: begin
aluOut <= 4'b1001; //Less than
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0110: begin
aluOut <= 4'b1010;
addi <= 1'b1; // addi
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1001: begin
aluOut <= 4'b0000;
FU <= 3'b010; // jf
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1011: begin
aluOut <= 4'b0000;
FU <= 3'b010; // jb
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b1;
end
4'b0011: begin // link
halt <= 1'b0;
RegEn <= 1'b0;
FU <= 3'b001;
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b1;
bank <= 2'b10;
js <= 1'b0;
end
4'b1100: begin
aluOut <= 4'b1010;
FU <= 3'b110; // branch
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1000: begin
aluOut <= 4'b0000;
FU <= 3'b000; // jumpreg
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0001: begin
aluOut <= 4'b0000;
mem <= 1'b1; // load
dataMemEn <= 1'b0;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
halt <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0010: begin
aluOut <= 4'b0000;
mem <= 1'b0; // store
dataMemEn <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1010: begin
halt <= 1'b0; // bank
RegEn <= !functBit;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= {functBit,functBit};
js <= 1'b0;
end
4'b0000: begin
halt <= 1'b1; // halt
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
default: begin
halt <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001;
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
always @(instIn, functBit)
begin
case(instIn)
4'b0000: // Halt/NOP
begin
halt <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0001: // Load Byte
begin
aluOut <= 4'b0000;
mem <= 1'b1;
dataMemEn <= 1'b0; // Disabled
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
halt <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0010: // Store Byte
begin
aluOut <= 4'b0000;
mem <= 1'b0;
dataMemEn <= 1'b1; // Enabled
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0011: // Link
begin
halt <= 1'b0;
RegEn <= 1'b0;
FU <= 3'b001;
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b1;
bank <= 2'b10;
js <= 1'b0;
end
4'b0100: // Zero
begin
aluOut <= 4'b1011;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0101: // Add/Subtract
if(functBit == 1) begin // Subtract
aluOut <= 4'b0001;
RegEn <= 1'b0;
FU <= 3'b001;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
else begin // Add
aluOut <= 4'b0000;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0110: // Add Immediate
begin
aluOut <= 4'b1010;
addi <= 1'b1;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0111: // Set if Less Than
begin
aluOut <= 4'b1001;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1000: // Jump to Register
begin
aluOut <= 4'b0000;
FU <= 3'b000;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1001: // Jump Forward
begin
aluOut <= 4'b0000;
FU <= 3'b010;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1010: // Bank Load/Bank Store
begin
halt <= 1'b0;
RegEn <= !functBit;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
aluOut <= 4'b0000;
dataMemEn <= 1'b0; // Disabled
mem <= 1'b0;
link <= 1'b0;
bank <= {functBit,functBit};
js <= 1'b0;
end
4'b1011: // Jump Backward
begin
aluOut <= 4'b0000;
FU <= 3'b010;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b1;
end
4'b1100: // Branch if Zero
begin
aluOut <= 4'b1010;
FU <= 3'b110;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1101: // NOR
begin
aluOut <= 4'b0011;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1110: // OR/AND
if(functBit == 1) // AND
begin
aluOut <= 4'b0100;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
else // OR
begin
aluOut <= 4'b0010;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1111: // Shift Right Logical/Shift Left Logical
if(functBit == 1) // Shift Right Logical
begin
aluOut <= 4'b0110;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
else // Shift Left Logical
begin
aluOut <= 4'b0101;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
default:
begin
halt <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001;
dataMemEn <= 1'b0; // Disabled
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
endcase
end
endmodule
module ControlUnit_tb();
reg [3:0] instruction;
reg functionB;
wire [3:0] aluOutput;
wire [2:0] FetchUnit;
wire addImmediate;
wire memory;
wire RegEnable;
wire addImmediate, memory, RegEnable;
ControlUnit ControlUnit0(
.instIn(instruction),

7
lab2CA.srcs/sources_1/new/RegFile.v
View File

@@ -1,6 +1,6 @@
`timescale 1ns / 1ps
module RegFile(input wire clk, reset, enable,
module RegFile(input wire clk, reset,
input wire [1:0] write_index, op0_idx, op1_idx,
input wire [8:0] write_data,
output wire [8:0] op0, op1);
@@ -11,7 +11,6 @@ module RegFile(input wire clk, reset, enable,
// To select a register En input must be 2'b00
decoder d0(
.en(enable),
.index(write_index),
.regOut(decOut)
);
@@ -67,7 +66,7 @@ endmodule
module regFile_tb();
reg [8:0] write_d;
reg [1:0] w_idx, op0_idx, op1_idx;
reg reset,clk, enable;
reg reset,clk;
wire [8:0] op0,op1;
initial begin
@@ -79,7 +78,6 @@ module regFile_tb();
RegFile regFile0(
.clk(clk),
.enable(enable),
.reset(reset),
.write_index(w_idx),
.op0_idx(op0_idx),
@@ -94,7 +92,6 @@ module regFile_tb();
reset = 1;
#5
reset = 0;
enable = 1;
w_idx = 2'b00;
op0_idx = 2'b00;
op1_idx = 2'b00;

280
lab2CA.srcs/sources_1/new/dataMemory.v
View File

@@ -6,24 +6,32 @@ module dataMemory(
output reg [8:0] readData
);
reg [8:0] memory [23:0];
reg [8:0] memory [512:0]; // Maximum of 512 memory locations
// Vivado will give warnings of unconnected ports on the "address" bus if they are unused
initial begin
//Equation Solver Memory
// memory[0] <= 9'b000000001;
// memory[1] <= 9'b000000010;
// String Compare Memory
// memory[0] <= 9'b000000100;
// memory[1] <= 9'b000001000;
// memory[2] <= 9'b000001100;
// memory[3] <= 9'b010101010;
// memory[4] <= 9'b000001111;
// memory[5] <= 9'b000000100;
// memory[6] <= 9'b000000000;
// memory[7] <= 9'b000000111;
// memory[8] <= 9'b000001111;
// memory[9] <= 9'b000000110;
// memory[0] <= 9'b000000100;
// memory[1] <= 9'b000001000;
// memory[2] <= 9'b000001100;
// memory[3] <= 9'b010101010;
// memory[4] <= 9'b000001111;
// memory[5] <= 9'b000000100;
// memory[6] <= 9'b000000000;
// memory[7] <= 9'b000000111;
// memory[8] <= 9'b000001111;
// memory[9] <= 9'b000000110;
// memory[10] <= 9'b000000010;
// memory[11] <= 9'b000000000;
// memory[12] <= 9'b000000000;
@@ -31,34 +39,39 @@ module dataMemory(
// memory[14] <= 9'b000000000;
// memory[15] <= 9'b000000000;
// Bubble Sort Initial Memory
memory[0] <= 9'b000010110;
memory[1] <= 9'b000100010;
memory[2] <= 9'b000100000;
memory[3] <= 9'b010001000;
memory[4] <= 9'b010010000;
memory[5] <= 9'b010011000;
memory[6] <= 9'b101001000;
memory[7] <= 9'b101001010;
memory[8] <= 9'b000100011;
memory[9] <= 9'b101001001;
memory[10] <= 9'b011001001;
memory[11] <= 9'b001001000;
memory[12] <= 9'b101001001;
memory[13] <= 9'b011101000;
memory[14] <= 9'b110001010;
memory[15] <= 9'b000100001;
memory[16] <= 9'b100110100;
memory[17] <= 9'b000001001;
memory[18] <= 9'b011001001;
memory[19] <= 9'b000110010;
memory[20] <= 9'b000000001;
memory[21] <= 9'b000111010;
memory[22] <= 9'b101011110;
memory[23] <= 9'b011111100;
// memory[0] <= 9'b000010110;
// memory[1] <= 9'b000100010;
// memory[2] <= 9'b000100000;
// memory[3] <= 9'b010001000;
// memory[4] <= 9'b010010000;
// memory[5] <= 9'b010011000;
// memory[6] <= 9'b101001000;
// memory[7] <= 9'b101001010;
// memory[8] <= 9'b000100011;
// memory[9] <= 9'b101001001;
// memory[10] <= 9'b011001001;
// memory[11] <= 9'b001001000;
// memory[12] <= 9'b101001001;
// memory[13] <= 9'b011101000;
// memory[14] <= 9'b110001010;
// memory[15] <= 9'b000100001;
// memory[16] <= 9'b100110100;
// memory[17] <= 9'b000001001;
// memory[18] <= 9'b011001001;
// memory[19] <= 9'b000110010;
// memory[20] <= 9'b000000001;
// memory[21] <= 9'b000111010;
// memory[22] <= 9'b101011110;
// memory[23] <= 9'b011111100;
// Binary Search Memory
// memory[0] <= 9'b000000000;
// memory[1] <= 9'b000000111;
// memory[2] <= 9'b000000001;
@@ -79,19 +92,160 @@ module dataMemory(
// memory[17] <= 9'b000010000;
// memory[18] <= 9'b000010001;
// memory[19] <= 9'b000010010;
// Program 1 Test Data
// memory[0] <= 9'd100;
// memory[1] <= 9'd58;
// memory[2] <= 9'd6;
// memory[3] <= 9'd12;
// memory[4] <= 9'b110110000; // -80
// memory[5] <= 9'd17;
// memory[6] <= 9'b111011011; // -37
// memory[7] <= 9'd25;
// memory[8] <= -9'd83; // -83
// memory[9] <= -9'd98; // -98
// memory[10] <= -9'd98; // -98
// memory[11] <= -9'd74; // -74
// memory[12] <= 9'd70;
// memory[13] <= -9'd38; // -38
// memory[14] <= 9'd52;
// memory[15] <= -9'd96; // -96
// memory[16] <= -9'd32; // -32
// memory[17] <= -9'd93; // -93
// memory[18] <= -9'd40; // -40
// memory[19] <= 9'd59;
// memory[20] <= 9'd10;
// memory[21] <= 9'd81;
// memory[22] <= -9'd23; // -28
// memory[23] <=- 9'd99; // -99
// memory[24] <= -9'd41; // -41
// memory[25] <= 9'd33;
// memory[26] <= 9'd98;
// memory[27] <= 9'd73;
// memory[28] <= -9'd1; // -1
// memory[29] <= 9'd28;
// memory[30] <= 9'd5;
// memory[31] <= -9'd74; // -74
// memory[32] <= -9'd41; // -41
// memory[33] <= 9'd41;
// memory[34] <= 9'd39;
// memory[35] <= 9'd62;
// memory[36] <= 9'd19;
// memory[37] <= -9'd40; // -40
// memory[38] <= -9'd8; // -8
// memory[39] <= 9'd92;
// memory[40] <= 9'd37;
// memory[41] <= 9'd50;
// memory[42] <= -9'd72; // -72
// memory[43] <= -9'd5; // -5
// memory[44] <= 9'd19;
// memory[45] <= 9'd58;
// memory[46] <= -9'd13; // -13
// memory[47] <= 9'd0;
// memory[48] <= -9'd97; // -97
// memory[49] <= 9'd54;
// memory[50] <= -9'd17; // -17
// memory[51] <= -9'd83; // -83
// memory[52] <= 9'd53;
// memory[53] <= 9'd82;
// memory[54] <= -9'd94; // -94
// memory[55] <= -9'd77; // -77
// memory[56] <= -9'd74; // -74
// memory[57] <= -9'd52; // -52
// memory[58] <= 9'd85;
// memory[59] <= -9'd65; // -65
// memory[60] <= -9'd10; // -10
// memory[61] <= -9'd45; // -45
// memory[62] <= -9'd92; // -92
// memory[63] <= -9'd30; // -30
// memory[64] <= 9'd18;
// memory[65] <= -9'd95; // -95
// memory[66] <= -9'd27; // -27
// memory[67] <= -9'd74; // -74
// memory[68] <= 9'd62;
// memory[69] <= 9'd64;
// memory[70] <= -9'd9; // -9
// memory[71] <= 9'd66;
// memory[72] <= -9'd71; // -71
// memory[73] <= -9'd31; // -31
// memory[74] <= 9'd34;
// memory[75] <= 9'd12;
// memory[76] <= 9'd3;
// memory[77] <= 9'd82;
// memory[78] <= 9'd13;
// memory[79] <= -9'd78; // -78
// memory[80] <= -9'd8; // -8
// memory[81] <= 9'd88;
// memory[82] <= 9'd42;
// memory[83] <= 9'd42;
// memory[84] <= 9'd21;
// memory[85] <= -9'd44; // -44
// memory[86] <= 9'd30;
// memory[87] <= -9'd93; // -93
// memory[88] <= 9'd2;
// memory[89] <= -9'd34; // -34
// memory[90] <= 9'd92;
// memory[91] <= -9'd45; // -45
// memory[92] <= 9'd26;
// memory[93] <= -9'd79; // -79
// memory[94] <= 9'd43;
// memory[95] <= -9'd25; // -25
// memory[96] <= -9'd24; // -24
// memory[97] <= -9'd25; // -25
// memory[98] <= -9'd19; // -19
// memory[99] <= -9'd49; // -49
// memory[100] <= -9'd8; // -8
// Program 2 Test Data
// memory[0] <= 9'd4;
// memory[1] <= 9'd15;
// memory[2] <= 9'b000001100;
// memory[3] <= 9'b010101010;
// memory[4] <= 9'h68; // h
// memory[5] <= 9'h65; // e
// memory[6] <= 9'h6C; // l
// memory[7] <= 9'h6C; // l
// memory[8] <= 9'h6F; // o
// memory[9] <= 9'h20; // <space>
// memory[10] <= 9'h77; // w
// memory[11] <= 9'h6F; // o
// memory[12] <= 9'h72; // r
// memory[13] <= 9'h6C; // l
// memory[14] <= 9'h64; // d
// memory[15] <= 9'h68; // h
// memory[16] <= 9'h65; // e
// memory[17] <= 9'h6C; // l
// memory[18] <= 9'h6C; // l
// memory[19] <= 9'h6F; // o
// memory[20] <= 9'h20; // <space>
// memory[21] <= 9'h77; // w
// memory[22] <= 9'h6F; // o
// memory[23] <= 9'h72; // r
// memory[24] <= 9'h6C; // l
// memory[25] <= 9'h64; // d
// Program 3 Test Data
// memory[0] <= 9'd25; // 25
// memory[1] <= -9'd3; // -3
end
always@(address, clk, memory)begin
if(clk == 1'b1)begin
readData <= memory[address];
if(writeEnable == 1'b1)begin
memory[address] <= writeData;
end
else begin
memory[address] <= memory[address];
end
end
always @ (posedge clk)
begin
if(writeEnable == 1'b1)
memory[address] <= writeData;
else
readData <= memory[address];
end
endmodule
@@ -100,12 +254,8 @@ module dataMemory_tb();
reg [8:0] address, writeData;
wire [8:0] readData;
initial begin
clk = 1'b0;
end
always begin
always
#5 clk = ~clk; // Period to be determined
end
dataMemory dM0(
.clk(clk),
@@ -115,7 +265,9 @@ module dataMemory_tb();
.readData(readData)
);
initial begin
initial
begin
clk = 1'b0;
writeEnable = 1'b0;
address = 9'b000000000;
writeData = 9'b010101010;
@@ -133,7 +285,27 @@ module dataMemory_tb();
address = 9'b000000010;
writeData = 9'b000000101;
#10
address = 9'b000000011;
writeEnable = 1'b0;
address = 9'b001000000;
writeData = 9'b010101010;
#10
address = 9'b001000001;
writeData = 9'b000001111;
#10
address = 9'b000011010;
writeData = 9'b000000101;
#10
writeEnable = 1'b1;
address = 9'b100111000;
writeData = 9'b010101010;
#10
address = 9'b100100001;
writeData = 9'b000001111;
#10
address = 9'b110000010;
writeData = 9'b000000101;
#10
address = 9'b111110011;
writeData = 9'b000000011;
#10
address = 9'b00000010;

156
lab2CA.srcs/sources_1/new/instructionMemory.v
View File

@@ -1,7 +1,6 @@
`timescale 1ns / 1ps
module instructionMemory(
input wire clk,
input wire [8:0] address,
output reg [8:0] readData
);
@@ -10,15 +9,12 @@ module instructionMemory(
initial begin
//Equation Solver
// memory[0] <= 9'b000000000;
// memory[1] <= 9'b011000000; //add0
// memory[1] <= 9'b011001001; //add1
// memory[1] <= 9'b000100000; //load
// memory[2] <= 9'b000101000; //load
// memory[3] <= 9'b010100010; //add
// memory[4] <= 9'b111100000; //shift left
// memory[5] <= 9'b111100000; //shift left
// memory[6] <= 9'b000000000; //halt
memory[0] <= 9'b000000000;
memory[1] <= 9'b000100000; //load
memory[2] <= 9'b000101000; //load
memory[3] <= 9'b010100010; //add
memory[4] <= 9'b111100000; //shift left
memory[5] <= 9'b111100000; //shift left
// //Testing all instructions
// memory[6] <= 9'b010100011; //sub
@@ -80,68 +76,68 @@ module instructionMemory(
// Bubble Sort
memory[0] <= 9'b000000001; // nop
// Setup
memory[1] <= 9'b010000000; // zero $a
memory[2] <= 9'b000100000; // lb $a, $a
memory[3] <= 9'b010001000; // zero $b
memory[4] <= 9'b010010000; // zero $c
memory[5] <= 9'b010011000; // zero $d
memory[6] <= 9'b101001000; // banks $b, $0
memory[7] <= 9'b101001010; // banks $b, $1
memory[8] <= 9'b100100011; // jf EndChk
// Increment current index to compare next pair of values
// Inc:
memory[9] <= 9'b101001001; // bankl $b, $0
memory[10] <= 9'b011001001; // addi $b, 1
memory[11] <= 9'b101001000; // banks $b, $0
// Check if at the end of the array
// EndChk:
memory[12] <= 9'b101001001; // bankl $b, $0
memory[13] <= 9'b011101000; // slt $b, $a
memory[14] <= 9'b110001001; // beq $b, JSC
memory[15] <= 9'b100100001; // jf LoadNext
// JSC:
memory[16] <= 9'b100110100; // jf SwapChk
// Load next values for comparison
// LoadNext:
memory[17] <= 9'b101001001; // bankl $b, $0
memory[18] <= 9'b011001001; // addi $b, 1
memory[19] <= 9'b000110010; // lb $c, $b
memory[20] <= 9'b011001001; // addi $b, 1
memory[21] <= 9'b000111010; // lb $d, $b
// Compare loaded values to see if they need to be swapped
memory[22] <= 9'b101011110; // banks $d, $3
memory[23] <= 9'b011111100; // slt $d, $c
memory[24] <= 9'b110011001; // beq $d, JI
memory[25] <= 9'b100100001; // jf Swap
// JI:
memory[26] <= 9'b101110010; // jb Inc
// Swap values in array
// Swap:
memory[27] <= 9'b101001001; // bankl $b, $0
memory[28] <= 9'b011001001; // addi $b, 1
memory[29] <= 9'b101011111; // bankl $d, $3
memory[30] <= 9'b001011010; // sb $d, $b
memory[31] <= 9'b011001001; // addi $b, 1
memory[32] <= 9'b001010010; // sb $c, $b
memory[33] <= 9'b010001000; // zero $b
memory[34] <= 9'b011001001; // addi $b, 1
memory[35] <= 9'b101001010; // banks $b, $1
memory[36] <= 9'b101111100; // jb Inc
// Check to see if any swaps have been made in the last iteration
// SwapChk:
memory[37] <= 9'b101001011; // bankl $b, $1
memory[38] <= 9'b110001001; // beq $b, JE
memory[39] <= 9'b100100001; // jf Reset
// JE:
memory[40] <= 9'b100100011; // jf End
// Reset:
memory[41] <= 9'b010001000; // zero $b
memory[42] <= 9'b101001000; // banks $b, $0
memory[43] <= 9'b101111011; // jb LoadNext
// End:
memory[44] <= 9'b000000000; // halt
// memory[0] <= 9'b000000001; // nop
// // Setup
// memory[1] <= 9'b010000000; // zero $a
// memory[2] <= 9'b000100000; // lb $a, $a
// memory[3] <= 9'b010001000; // zero $b
// memory[4] <= 9'b010010000; // zero $c
// memory[5] <= 9'b010011000; // zero $d
// memory[6] <= 9'b101001000; // banks $b, $0
// memory[7] <= 9'b101001010; // banks $b, $1
// memory[8] <= 9'b100100011; // jf EndChk
// // Increment current index to compare next pair of values
// // Inc:
// memory[9] <= 9'b101001001; // bankl $b, $0
// memory[10] <= 9'b011001001; // addi $b, 1
// memory[11] <= 9'b101001000; // banks $b, $0
// // Check if at the end of the array
// // EndChk:
// memory[12] <= 9'b101001001; // bankl $b, $0
// memory[13] <= 9'b011101000; // slt $b, $a
// memory[14] <= 9'b110001001; // beq $b, JSC
// memory[15] <= 9'b100100001; // jf LoadNext
// // JSC:
// memory[16] <= 9'b100110100; // jf SwapChk
// // Load next values for comparison
// // LoadNext:
// memory[17] <= 9'b101001001; // bankl $b, $0
// memory[18] <= 9'b011001001; // addi $b, 1
// memory[19] <= 9'b000110010; // lb $c, $b
// memory[20] <= 9'b011001001; // addi $b, 1
// memory[21] <= 9'b000111010; // lb $d, $b
// // Compare loaded values to see if they need to be swapped
// memory[22] <= 9'b101011110; // banks $d, $3
// memory[23] <= 9'b011111100; // slt $d, $c
// memory[24] <= 9'b110011001; // beq $d, JI
// memory[25] <= 9'b100100001; // jf Swap
// // JI:
// memory[26] <= 9'b101110010; // jb Inc
// // Swap values in array
// // Swap:
// memory[27] <= 9'b101001001; // bankl $b, $0
// memory[28] <= 9'b011001001; // addi $b, 1
// memory[29] <= 9'b101011111; // bankl $d, $3
// memory[30] <= 9'b001011010; // sb $d, $b
// memory[31] <= 9'b011001001; // addi $b, 1
// memory[32] <= 9'b001010010; // sb $c, $b
// memory[33] <= 9'b010001000; // zero $b
// memory[34] <= 9'b011001001; // addi $b, 1
// memory[35] <= 9'b101001010; // banks $b, $1
// memory[36] <= 9'b101111100; // jb Inc
// // Check to see if any swaps have been made in the last iteration
// // SwapChk:
// memory[37] <= 9'b101001011; // bankl $b, $1
// memory[38] <= 9'b110001001; // beq $b, JE
// memory[39] <= 9'b100100001; // jf Reset
// // JE:
// memory[40] <= 9'b100100011; // jf End
// // Reset:
// memory[41] <= 9'b010001000; // zero $b
// memory[42] <= 9'b101001000; // banks $b, $0
// memory[43] <= 9'b101111011; // jb LoadNext
// // End:
// memory[44] <= 9'b000000000; // halt
// Binary Search
@@ -213,28 +209,16 @@ module instructionMemory(
end
always@(address, clk)begin
if(clk == 1'b1)begin
readData <= memory[address];
end
end
always @ (address)
readData <= memory[address];
endmodule
module instructionMemory_tb();
reg clk;
reg [8:0] address;
wire [8:0] readData;
initial begin
clk = 1'b0;
end
always begin
#5 clk = ~clk; // Period to be determined
end
instructionMemory iM0(
.clk(clk),
.address(address),
.readData(readData)
);